WISER: Systematic Design-Space Exploration of Trapped Ions with Multiplexed Control

AI summary

Overview

Research area: Quantum computing architecture, specifically trapped-ion Quantum Charge-Coupled Devices (QCCD) with multiplexed control, quantum error correction (QEC), and compilation for fault-tolerant quantum computing (FTQC). Technical level: Advanced. The paper assumes familiarity with trapped-ion shuttling, stabiliser codes, SAT solving, and logical error-rate simulation. Scope: A cross-layer framework, WISER, that couples a WISE-specific SAT compiler, a physics-informed noise model, and logical-memory simulation to evaluate how multiplexing order, trap capacity, cooling policy, and QEC family affect logical error rates, logical clock speed, and control power.

What This Paper Is About

Trapped-ion QCCD systems are difficult to scale because each ion needs roughly 10–100 electrodes and dedicated digital-to-analogue converter (DAC) control, creating wiring and power bottlenecks. The WISE architecture reduces this burden by sharing waveform generation and using integrated cryogenic switching, but it imposes global odd-even ion movement, limited parallelism, and sample-and-hold electrode charging. This paper asks whether WISE-style machines can support fault-tolerant quantum computation, and which multiplexing factors, trap capacities, cooling policies, and QEC codes are practical.

Key Contributions

1. An integrated design-space exploration framework. WISER combines a WISE-specific compiler, a physics-informed noise model that traces errors back to ion number, trap capacity, multiplexing order, and technology tier, and Stim-based logical-memory simulation that reports logical error rate, logical cycle time, and DAC power.
2. A SAT-based compiler for WISE routing. The compiler encodes WISE's globally broadcast odd-even swap primitives and asymmetric horizontal/vertical transport costs in a single SAT formulation. It produces schedules that are provably optimal within the encoded routing model when the search converges, and carries a proven lower bound otherwise. It reduces routing time by 2.6–18.8× relative to a greedy WISE-compatible baseline.
3. Concrete hardware guidance. The paper identifies two-ion traps with 16-way multiplexing, 8× lower than the original WISE proposal of M=128, as giving the fastest logical clock that meets its reliability and cold-stage power targets. It reports that laser cooling before every gate block is preferred in 18 of 20 feasible combinations of technology tier, error target, and objective.
4. A QEC and physical-parameter comparison. Across evaluated code families, including surface, colour, Bacon-Shor, and BB/qLDPC codes, the paper finds that with current hardware parameters the distance-7 surface code is the only evaluated code to meet its early-FTQC screen, and it identifies state preparation and measurement (SPAM), ion transport, and recooling as dominant design targets.

Main Findings

• Multiplexing order matters more than the original proposal assumed. The original WISE proposal used M=128-way multiplexing. WISER finds M=16 preferable: it keeps 98.5% of the unmultiplexed logical clock speed at 6.9% of the DAC power. With transport and cooling removed, M=16 keeps a syndrome-extraction round within 1.5–2.0× of the unmultiplexed round, compared with 5–10× at M=128.
• Two-ion traps are best for early FTQC. Among trap capacities k ∈ {2, 4, 6, 8, 16}, two-ion traps give the best logical clock speed and power. The paper notes this matches recent QCCD trap-capacity results even though the control system is drastically different.
• Surface codes are the only evaluated family that passes the early-FTQC screen with current hardware models. The distance-7 surface code passes at 4.58 Hz using 2.04 W of DAC power per logical qubit at M=16. Surface codes offer the fastest executions, while the high encoding rate of BB codes gives the lowest power per logical qubit.
• Transport and recooling dominate the cycle. At the stated operating point, ion transport and recooling take 94–96% of the WISE cycle. Even without them, sample-and-hold electrode charging leaves millisecond-scale syndrome-extraction rounds.
• Transport and cooling must be improved together. Neither shortening transport nor shortening recooling alone gives more than a 2.8× speed-up, because together they account for most of the cycle.
• SPAM is a high-leverage target. Improving state preparation and measurement from 10⁻⁴ to 10⁻⁵ alone removes 70% of the expected physical faults of a syndrome round.
• Shared control imposes a scaling penalty outside WISE as well. With all transport and cooling removed, multiplexed control with non-overlapped charging lengthens a surface-code syndrome-extraction round from 1.3 ms to 6.7 ms when going from M=1 to M=128 on current hardware.
• The cryptography outlook is demanding. At these round times, recovering a P-256 elliptic-curve private key within 48 hours, using the same number of logical rounds as a recent neutral-atom estimate, requires a 260× reduction in logical circuit depth, rising to 4,100× once WISE's transport and recooling are included.
• Cooling policy is consistent across feasible configurations. Cooling before every gate block, corresponding to a phonon threshold of zero, is preferred in 18 of 20 feasible combinations of technology tier, error target, and objective, consistent with current experimental practice.

Methodology in Plain English

WISER starts with a QEC code specification and a hardware configuration: number of ions, trap capacity, multiplexing order, phonon threshold, and technology tier. The QEC circuit is written in Stim format, lowered into WISE's native operations (MS entangling gates, rotations, measurement, and reset), then mapped and routed onto the physical grid.

Routing is solved with a SAT formulation. The solver decides where every ion sits at each routing pass and which odd-even swaps fire, subject to WISE's broadcast parity rules. The objective minimises weighted routing time rather than raw swap count, because vertical movement through shared junctions is much more expensive than horizontal movement. A cycle-reuse decomposition encodes one repeated syndrome-extraction cycle plus a route-back round, then replays that solution, which makes large code distances tractable. A parallel search tightens both feasible schedules and lower bounds.

A physics-aware scheduler then interleaves reconfiguration, gate blocks, and cooling. A per-ion phonon tracker estimates motional excitation from transport, gates, and idling; when any trap exceeds the phonon threshold, all traps are cooled simultaneously because WISE uses single-instruction, multiple-data control. Gate layers also wait for multiplexed electrode charging, modelled as a fixed latency proportional to M.

The noise model assigns error rates to each gate at the live phonon state of its trap, rather than using fixed per-gate-type error rates. It accounts for motional heating, phonon generation during transport and swapping, crosstalk from shared motional modes, shared-DAC control noise, and constant single-qubit, measurement, and reset penalties. These channels are injected into a Stim simulation, decoded, and used to estimate the logical error rate; the schedule supplies the logical cycle time, and a power model counts every zone in the chosen grid, including unused ones.

Why This Matters

This work connects device-level trapped-ion physics with system-level QEC design. It gives hardware architects a quantitative basis for choosing multiplexing order, trap size, and cooling policy, and it gives QEC researchers a way to ask which code families survive realistic control constraints rather than abstract noise models. It also shows that the intuitively appealing direction of more multiplexing is not necessarily better for logical performance.

Real-world applications of fault-tolerant quantum computing cited in the paper:

• Cryptography: RSA factoring and elliptic-curve key recovery, including the P-256 estimate.
• Quantum chemistry: simulating molecular and materials systems beyond classical reach.
• Materials science: computing properties of new materials.
• Optimisation: solving problems that are intractable for classical computers.

Industry relevance: WISE is being actively pursued by IonQ/Oxford Ionics, and the paper's cooling assumptions mirror the frequent recooling used in Quantinuum's H-series and Helios systems. The finding that M=16 rather than M=128 is preferable, and that two-ion traps perform best, is directly relevant to groups designing multiplexed-control trapped-ion machines. The compiler and noise model are also relevant to teams building architecture-level tooling for QEC.

Future Directions

• Overlap electrode charging with other operations. The scheduler currently does not overlap sample-and-hold charging with gates or transport. The paper identifies this as a way to shorten gate layers and notes it is not modelled.
• Model correlated faults across shared DACs. The noise model uses shared-control physics to set error rates but samples faults independently per gate. Since electrodes sharing a DAC experience identical voltage noise, spatially correlated errors across distant qubits remain a failure mode that standard QEC analyses do not capture.
• Co-design shorter transport and recooling together. Because neither alone yields more than a 2.8× speed-up, the paper points to joint improvements in shuttling and cooling as necessary for practical FTQC timelines.
• Evaluate more code families and control-sharing proposals. The paper examines surface, colour, Bacon-Shor, and BB/qLDPC codes, and focuses on WISE as the most aggressive DAC-sharing proposal. Other DAC-sharing architectures and additional QEC families remain open to comparison within the same framework.

Target Audience

This paper is most useful to quantum architecture researchers, trapped-ion hardware designers, QEC theorists interested in code-to-device mapping, and compiler researchers working on exact routing for quantum processors. It also benefits industry teams evaluating multiplexed-control scalability and readers who want a quantitative bridge between component-level trapped-ion physics and fault-tolerant system design.

Authors’ abstract

Trapped-ion Quantum Charge-Coupled Devices (QCCD) are a leading contender for quantum computing, but their scalability is constrained by control wiring and electronics. Wiring using Integrated Switching Electronics (WISE), a recently proposed QCCD architecture, reduces wiring through multiplexing and integrated switching hardware. However, this leaves an execution model with limited parallelism and limited flexibility in ion movement. Further, these devices need to be paired with a quantum error correction (QEC) code to enable fault-tolerant quantum computation (FTQC). Can WISE architectures efficiently support FTQC requirements? Which QEC choices, device and control parameters are practical? We present WISER, a cross-layer design-space exploration framework for trapped-ion systems with multiplexed control. WISER combines a WISE-specific SAT-based compiler, a physics-informed noise model and logical-memory simulation to estimate logical error rates, logical clock speeds and control power across hardware parameters and QEC families. Its compiler reduces routing time by $2.6$--$18.8\times$ relative to a greedy WISE-compatible baseline. Our analysis provides concrete design guidance. Two-ion traps with $16$-way multiplexing, $8\times$ lower than the original WISE proposal, give the fastest logical clock that meets our reliability and cold-stage power targets. With current hardware parameters, the distance-7 surface code is the only evaluated code to meet our early-FTQC screen, at $4.58\,$Hz and $2.04\,$W of DAC power per logical qubit. At this operating point, ion transport and recooling take $94$--$96\%$ of the WISE cycle, and even without them sample-and-hold electrode charging leaves millisecond-scale syndrome-extraction rounds.