Stitched surface codes: planar concatenation through GHZ corridors

AI summary

Overview

Research area: Quantum error correction for superconducting quantum processors — specifically concatenated/stitched surface-code architectures with hardware-efficient planar connectivity.

Technical level: Advanced. The paper assumes familiarity with stabilizer codes, CSS codes, detector error models, and minimum-weight perfect matching. The plain-language sections below translate the core results, but the underlying construction is specialist material.

Scope: The paper proposes, simulates, and experimentally demonstrates a concatenated quantum memory that stitches four rotated surface-code patches into the smallest non-trivial outer code, the [[4,2,2]] code, measuring the outer stabilizers through GHZ ancilla "corridors" on a 105-qubit Willow processor.

What This Paper Is About

Standard rotated surface codes encode one logical qubit per patch, so protecting two logical qubits at distance d requires two separate patches and roughly 2(2d²−1) physical qubits. The authors ask whether four smaller distance-t patches can be combined into one block that encodes two logical qubits at distance d = 2t, on the same square lattice with nearest-neighbor connectivity, and whether the combination uses fewer qubits than two independent patches. Their answer is a "stitched" code assembled from four rotated surface-code patches and the [[4,2,2]] outer code, with the outer stabilizers measured via Greenberger–Horne–Zeilinger (GHZ) states prepared and verified in narrow ancilla corridors running between the patches.

Key Contributions

1. A planar concatenated architecture. Four distance-t rotated surface-code patches are concatenated with the [[4,2,2]] outer code, producing a [[4t², 2, 2t]] code of distance d = 2t with k = 2 logical qubits, occupying N = 2d² + 4d − 3 physical qubits on a square lattice with nearest-neighbor connectivity (the abstract states the footprint as N < 2(2t+1)²). At the worked example t = 3, N = 93, k = 2, d = 6.

2. GHZ corridors instead of lattice surgery. The two outer-code stabilizer generators, XXXX and ZZZZ, each of physical weight 4t, are measured in situ using verified GHZ resource states that thread between adjacent patches. Corridor overhead is 8t + 1 qubits, growing only linearly with t. Corridor qubits adjacent to each patch double as weight-two boundary ancillae, temporarily disabling those boundary checks during corridor rounds.

3. A matchable detector error model despite hyperedges. Corridor faults can flip detectors in the corridor and in multiple patches at once — hyperedges that normally require BP+OSD or a search-based decoder such as Tesseract. The authors design the corridor checks and verifiers so every such mechanism decomposes into graphlike components, allowing a single PyMatching MWPM pass (optionally correlated reweighting) over all four patches.

4. Simulation and hardware demonstration. Circuit-level Stim simulations under the SI1000 model show logical error rates scaling as p^t, consistent with distance 2t. The construction was then run experimentally at d = 4 and d = 6 on a 105-qubit Willow superconducting processor in both Z and X memory bases.

Main Findings

• Distance-product bound is saturated. The explicit construction achieves d = 2t for the concatenated code, exactly matching the bound d ≥ d_o·d_i from the outer code's distance 2 and the inner patch's distance t.

• Encoding density doubles asymptotically. The ratio k d²/N → 1 as t → ∞, which the authors state is twice the single-patch ratio of 1/2. At equal distance, the stitched layout is said to save 2d² − 4d + 1 qubits relative to two independent distance-d patches.

• Verification depth sets the circuit distance. For t ≤ 10 and r_v ≥ 2, distances computed with Stim follow d_circ = min(2t, r_v + 3), so the design distance 2t is reached at r_v = 2t − 3. Stim results are confirmed exactly by exhaustive cluster enumeration for d_circ ≤ 7, with upper bounds at larger distances also agreeing.

• Verification depth has an optimum that shifts with error rate. At t = 7 under SI1000, the best r_v moves from r_v = 2–3 at p = 4×10⁻³ to r_v = 4 at p = 10⁻³, because a longer outer-code round raises measurement noise, extends the window in which boundary weight-two detectors are disabled, and adds latency.

• Scaling follows p^t. Simulations cover d = 4, 6, 8, 10, 14 for the stitched code against d = 3, 5, 7, 9, 13 for two surface-code patches under SI1000, with the uniform depolarizing comparison in an appendix. The stitched code's logical error rate scales with slope t on log-log axes.

• Footprint advantage is conditional, not universal. The stitched code beats two surface-code patches in qubits-to-target-error at N ≈ 157 for p = 10⁻⁴, N ≈ 237 for p = 5×10⁻⁴, and N ≈ 333 for p = 10⁻³. At p = (2–3)×10⁻³, its logical error rate at N ≈ 10³ is still 10–14% higher than two surface-code patches. The authors note their own hardware error rates lie above this crossover.

• Hardware shows below-threshold improvement from d = 4 to d = 6. On the 105-qubit Willow processor, increasing code distance from d = 4 to d = 6 reduces the block logical error rate by a factor of 1.52 with the correlated-matching decoder.

• Experimental circuit parameters. The d = 4 run used t = 2 and r_v = 1 (four inner cycles per full outer-code cycle); the d = 6 run used t = 3 and r_v = 2 (six inner cycles), giving d_circ = 5, smaller than the code distance of 6. Rounds r_o ∈ {1, …, 8} correspond to τ ∈ {7, 11, …, 35} inner cycles for t = 2 and τ ∈ {10, 16, …, 52} for t = 3; each circuit was sampled with 200,000 shots.

• The two logical channels are correlated. A single independent error rate fits either logical observable separately but fails for the block error rate, so the data are fitted with a four-state continuous-time Markov chain with rates μ₀₁, μ₁₀, and μ₁₁. For example, the reported MWPM rates at d = 4 are μ₀₁ = 2.065(14), μ₁₀ = 2.032(14), μ₁₁ = 2.123(14) in the Z basis and 2.933(23), 2.605(23), 2.610(23) in the X basis; the table of d = 6 rates is cut off in the supplied text.

• Correlated matching improves accuracy. For the hardware data, correlated matching outperformed plain MWPM on the same measured sets, so only correlated-matching results are plotted.

• Hardware demands are higher than a native memory experiment. Some qubits normally used as data qubits are repurposed as corridor ancillae and must be measured and reset every outer-code extraction round, on a device whose sublattices were optimized for the native bipartite surface-code layout. Data-qubit leakage removal (DQLR) is applied at the boundaries of each GHZ block.

Methodology in Plain English

The researchers take four small surface-code patches and arrange them in the four quadrants of a square. Between the patches they leave narrow lanes of spare qubits — the corridors. To measure a joint operator across all four patches, they prepare a long entangled (GHZ) state along a corridor, check it, couple it to the patches, and read it out. This replaces lattice surgery, which would normally be needed to entangle separate patches.

Preparing a long GHZ state is delicate: a single mistake during preparation can spread into a multi-qubit error on the data once the state is coupled in. So before using each GHZ state, they run several verification rounds that measure neighbouring-pair parities along the corridor, catching the dangerous X errors while harmless Z errors just flip the readout. The parity information from preparation is absorbed into the detector bookkeeping rather than actively corrected in the circuit.

For decoding, they extract a detector error model from the circuit and check that every fault mechanism splits into pieces that each flip at most two detectors. That makes the whole thing matchable in one PyMatching call. They then run Monte Carlo simulations with Stim under two noise models, sweeping distance, verification depth, and physical error rate, and compare against two independent surface-code patches on both logical error rate and qubit footprint. Finally, they compile two instances of the circuit (d = 4 and d = 6) onto a 105-qubit Willow chip, run memory experiments in both bases over a range of round counts, decode with correlated matching, and fit the decay of logical error with time using a four-state Markov model that accounts for the two logical channels failing together.

Why This Matters

Concatenation and quantum LDPC codes can in principle beat the surface code on encoding rate, but most constructions assume connectivity that fixed superconducting lattices do not have. This work shows a concatenated code that stays planar, uses only nearest-neighbor gates, and — importantly — is small enough to actually run on today's hardware rather than only in the large-scale fault-tolerant regime. It also demonstrates a route to measuring high-weight stabilizers via verified GHZ states rather than lattice surgery, and it keeps the decoder practical by enforcing a graphlike error model, which matters for real-time decoding at hardware cycle times.

Real-world applications (long-term, since these are enabling technologies rather than end products):

• Quantum chemistry and materials simulation on fault-tolerant superconducting machines, where logical qubit overhead directly determines what system sizes are reachable.
• Cryptographic and optimization workloads that need many logical qubits at modest distance rather than a single very well-protected one.
• Hardware benchmarking and calibration — the stitched layout serves as a near-term diagnostic that stresses repeated measurement and reset on qubits not optimized for it.
• Real-time decoder engineering — the graphlike-by-design approach informs how future control electronics allocate decoding latency budgets.

Industry relevance: the authors are at Google Quantum AI, and the experiment runs on the same Willow processor family used for that group's below-threshold surface-code memory work. A construction that trades a modest footprint advantage for a testable concatenated architecture is directly relevant to roadmaps that must decide between scaling surface-code patches and moving to higher-rate codes.

Future Directions

• Push to lower physical error rates. The footprint advantage only appears below the measured crossovers (N ≈ 157 at p = 10⁻⁴, N ≈ 237 at p = 5×10⁻⁴, N ≈ 333 at p = 10⁻³); the reported hardware error rates sit above them, so improved devices are needed to realize the qubit savings experimentally.

• Run at larger distance with more verification. The d = 6 experiment used r_v = 2, giving d_circ = 5 rather than the design distance of 6; raising r_v to 2t − 3 at lower p would test the full 2t protection on hardware.

• Exploit the transversal Clifford structure. The paper notes that transversal CNOT between two [[4,2,2]] blocks, a transversal Hadamard, qubit permutations realizing CNOT within a block, and a transversal phase-gate pattern realizing CZ are available — but states these are not used in this work, leaving logical-gate demonstrations open.

• Decoder and hyperedge handling at scale. The current design deliberately avoids hyperedges to allow single-pass MWPM; whether correlated matching or faster native hyperedge decoders (BP+OSD, Tesseract) become practical at hardware cycle times remains an open engineering question.

• Extend the modular approach. The discussion section is said to cover geometric and modular advantages, experimental considerations, and open problems, but the specific contents are not included in the supplied text.

Target Audience

Specialists in quantum error correction and superconducting quantum hardware: researchers designing fault-tolerant architectures, hardware teams evaluating concatenated versus monolithic surface-code scaling, and decoder engineers concerned with detector error models and real-time matching. Experimentalists planning below-threshold memory demonstrations on fixed-connectivity devices will find the scheduling and boundary-ancilla-reuse details directly useful. Readers without a stabilizer-code background will find the paper demanding, though the architectural idea — four patches plus GHZ corridors — is accessible at a conceptual level.

Authors’ abstract

We present a fault-tolerant quantum-memory architecture that concatenates four distance-t rotated surface-code patches with the [[4,2,2]] outer code, encoding two logical qubits at code distance d = 2t in a physical footprint of N &lt; 2(2t+1)^2 qubits on a square lattice with nearest-neighbor connectivity. The outer-code stabilizer generators XXXX and ZZZZ, each of physical weight 4t, are measured in situ via verified Greenberger-Horne-Zeilinger (GHZ) ancillae distributed through narrow corridors between adjacent patches, without lattice surgery or long-range gates. The outer-code gadgets introduce hyperedge fault mechanisms, but by design each decomposes into graphlike components, so the complete syndrome is decoded by a single minimum-weight-perfect-matching pass. Circuit-level simulations show logical error rates that scale as p^t, consistent with distance-2t protection. Finally, we implement the construction experimentally on a 105-qubit Willow superconducting processor in both the ZZ and XX memory bases. With the correlated-matching decoder, increasing the code distance from d = 4 to d = 6 reduces the block logical error rate by a factor of 1.52. The construction thus provides a near-term testbed for concatenated architectures beyond the standard surface code.