Quantum Circuit Pruning: From NISQ Architectures to Fault-Tolerant Operations

AI summary

Overview

Research area: Quantum computing compilation and circuit optimization, specifically the removal ("pruning") of parametric two-qubit gates, evaluated across both noisy intermediate-scale quantum (NISQ) hardware and fault-tolerant quantum computing (FTQC) architectures based on lattice surgery.

Technical level: Intermediate. The paper is written clearly and develops its argument from a single fidelity bound, but it assumes familiarity with qubit routing, SWAP insertion, surface codes, and logical error rates.

Scope (one sentence): The paper proposes a single routing-aware pruning criterion — comparing an architecture-independent bound on the fidelity lost by omitting a gate against a hardware-specific model of the cost of executing it — and evaluates it on NISQ benchmarks and on simulated lattice-surgery fault-tolerant hardware.

What This Paper Is About

Quantum circuits often contain controlled rotation gates with very small rotation angles, which behave almost like the identity and therefore change the quantum state very little. Executing such a gate on distant qubits, however, can be expensive: on NISQ devices it requires chains of SWAP gates that add noise, and on fault-tolerant devices it requires long merge-split paths whose logical error rate grows with distance. The paper's goal is to decide, gate by gate and during compilation, whether the small computational contribution of a rotation is outweighed by the cost of routing it — and to show that one criterion works in both hardware regimes.

Key Contributions

1. A routing-aware pruning criterion. Each parametric two-qubit gate is judged by comparing an architecture-independent lower bound on the fidelity cost of omitting it, cos²(θ/2) (Theorem 1), against a hardware-specific model of the fidelity cost of executing it. The decision is made during routing, using the actual qubit positions at compilation time rather than an abstract pre-routing estimate.

2. A unified NISQ-to-FTQC framework. The NISQ case models cost through depolarizing noise accumulated by SWAP chains, with a closed-form expression for the fidelity of routed execution. The fault-tolerant case models cost through the logical error rate of the lattice-surgery merge-split path. Only the cost model changes between regimes; the omission bound is reused unmodified.

3. An analytical characterization of the pruning boundary. The paper derives, from the NISQ cost expression, the critical routing distance d* beyond which a gate is pruned, as a joint function of rotation angle θ, qubit distance, and two-qubit gate error rate p₂ — giving compiler designers a way to anticipate pruning behavior without simulation.

4. Empirical evaluation in both regimes. Density-matrix simulation on MQT Bench circuits of 4 to 14 qubits compiled to grid topologies, plus a fault-tolerance feasibility study using Stim, PyMatching, and TQEC across code distances d_code ∈ {3, 5, 7, 9, 11} and physical error rates p ∈ {10⁻³, 5×10⁻⁴, 10⁻⁴}.

Main Findings

• NISQ gate reduction: Pruning reduces two-qubit (CX) gate counts by up to 48.6% on the benchmark suite.

• NISQ fidelity gain: Final state fidelity improves by up to 47.7% relative to the unpruned noisy baseline, measured against an ideal noiseless state.

• Algorithm-dependent consistency: Improvements are consistent across all circuit sizes for Amplitude Estimation and QFT. For QAOA, results are less consistent, and overly aggressive pruning at 10 qubits produced a net fidelity degradation, attributed to the fixed 1.25× SWAP-overhead approximation underestimating how efficiently the mapper batches SWAPs for QAOA's dense structure.

• Pruning boundary scales as expected: The critical distance d* grows with rotation angle θ and shrinks as the two-qubit error rate p₂ improves. At current NISQ noise levels (p₂ ∼ 10⁻³), an angle as large as θ = π/8 is pruned at d* ≈ 20. As p₂ approaches ∼10⁻⁶, only near-identity rotations (θ ≲ π/256) remain candidates, and only at distances ≤ 250.

• FT pruning window exists but narrows: At p = 10⁻³, a moderate code distance such as d_code = 7 already exceeds the pruning threshold for small-angle rotations at separations beyond a few tens of patches. At p = 10⁻⁴, only very small angles enter the pruning regime, and only as code distance increases — better hardware narrows but does not eliminate the window.

• Comparison with offline pruning: The method matches the fidelity of the best offline approximation degree for the QFT circuit in the authors' prior work, without requiring an exhaustive search over approximation degrees.

Methodology in Plain English

The approach rests on one intuition: a rotation by a small angle θ moves a quantum state very little, and the paper proves a worst-case guarantee that the overlap between the rotated and unrotated states is at least cos²(θ/2). That quantity depends only on the angle, so it is the same on any hardware and serves as the "cost of deleting the gate."

Against that, the compiler computes what it would cost to actually run the gate at its current location.

• On NISQ hardware, two distant qubits must be brought together using SWAP gates, each built from three CNOTs, each carrying depolarizing noise p₂. The number of SWAPs each qubit must undergo is half the separation distance, rounded up. Plugging this into a standard depolarizing fidelity model gives an execution fidelity, which is compared with cos²(θ/2). If execution is worse than deletion, the gate is dropped. Because routing heuristics insert more SWAPs than the minimum, the authors scale the estimated overhead by 1.25× when compiling with Route-Forcing, based on that mapper's reported 1.2–1.3× excess.

• On fault-tolerant hardware, the same comparison is made, but the execution cost comes from the logical error rate of the lattice-surgery path connecting two logical qubit patches. Longer paths cross more ancilla patches and accumulate more error. The authors simulate this with Stim and PyMatching, using up to 10⁹ shots per point, and use two logical CNOTs as a proxy for a parametric gate, since parametric gates are not native and must be decomposed that way. Single-qubit rotations in that decomposition are deliberately excluded from the cost, so the reported logical error rate is a lower bound on true execution cost.

For the NISQ evaluation, circuits from MQT Bench (4 to 14 qubits) are routed with Route-Forcing onto grid topologies, decomposed into IBM's native gate set {CX, ID, RZ, SX, X}, and simulated exactly at the density-matrix level under a noise model combining depolarizing two-qubit noise with thermal relaxation times T₁ and T₂ proportional to circuit duration. Three states are compared: ideal (noiseless), noisy (compiled, unpruned), and pruned.

Why This Matters

The work reframes circuit approximation as a hardware-aware decision rather than a purely mathematical one. Most existing pruning methods run before routing and look only at the rotation angle, ignoring the connectivity constraints that often dominate the error budget. By making the decision inside the compilation flow, the same simple criterion adapts automatically to the device's topology and noise level — and, notably, carries over to fault-tolerant hardware with only the cost model swapped out.

Real-world applications (drawn from the application areas the paper identifies for quantum computing generally):

• Chemistry and materials simulation, where deep circuits with many small-angle rotations are common and routing overhead accumulates quickly.
• Optimization, including QAOA-style workloads, which the paper tests directly and where it also identifies a failure mode of overly aggressive pruning.
• Cryptography, where long-range interactions stress the connectivity of sparse devices.
• Machine learning, where circuit depth and gate count directly limit what can run before decoherence dominates.

Industry relevance: Compiler and hardware vendors targeting superconducting grids must trade gate count against routing cost on every compilation. A pruning rule that needs no pre-tuning of approximation parameters, and that degrades gracefully as hardware noise improves, is straightforward to integrate into existing transpilation pipelines. The fault-tolerant analysis also speaks to resource estimation: the paper notes that single-qubit rotations in the parametric gate decomposition must be implemented via T-state injection after distillation, currently the largest time and resource bottleneck in fault-tolerant estimates, so reducing the number of retained rotations has direct resource implications.

Future Directions

• End-to-end fault-tolerant evaluation. The FT analysis is explicitly a feasibility study on logical CNOT pairs, not a full compiled algorithm. The authors state that applying the framework to full FT circuits remains to be done, as the required simulation tools are not currently available.

• Coupling pruning to magic state distillation. Because the single-qubit rotations attached to each parametric gate require distilled T states, the authors expect end-to-end FT results to have strong implications tied to distillation cost.

• Better routing-cost estimates. The QAOA degradation at 10 qubits traces to the fixed 1.25× SWAP-overhead assumption. A mapper-aware or dynamic estimate of how effectively SWAPs can be batched could remove this failure mode.

• Generalization beyond surface code plus lattice surgery. The authors state the methodology is not specific to any code or logical-gate scheme, including transversal gates; only the execution-cost model F_FT must be benchmarked per code and gate implementation.

Target Audience

Quantum compiler and transpiler engineers; researchers working on qubit mapping and circuit approximation; architects of NISQ and fault-tolerant hardware who need to reason about where routing overhead dominates; and graduate students or practitioners with some background in quantum circuit compilation who want a compact, self-contained example of how a single fidelity bound can drive decisions across two very different hardware regimes. Readers seeking full fault-tolerant algorithm benchmarks should note that this paper provides a feasibility analysis rather than end-to-end FT results.

Authors’ abstract

We present a routing-aware pruning strategy for quantum circuits that selectively removes parametric two-qubit gates whose computational contribution is outweighed by the fidelity cost of their execution, and assess it across both Noisy Intermediate-Scale Quantum (NISQ) and fault-tolerant quantum computing (FTQC) architectures. Each two-qubit gate of a circuit is evaluated by comparing an architecture-independent lower bound on the fidelity cost of omitting the gate against a hardware-specific model for the routing execution cost in each setting. We additionally provide an analytical characterization of the pruning boundary as a function of rotation angle, qubit distance, and hardware noise. Simulations on benchmark circuits demonstrate gate count reductions of up to 48.6% and fidelity improvements of up to 47.7% in the NISQ regime, while a feasibility analysis on FT hardware indicates that pruning is expected to remain relevant across a range of code distances and physical error rates. These results establish routing-aware pruning as a practical and unified compilation strategy across the quantum computing stack.