Qu-Trefoil: Large-Scale Quantum Circuit Simulator Working on FPGA With SATA Storages

AI summary

Overview

• Research area: Quantum physics / quantum computing hardware — state-vector quantum circuit simulation on reconfigurable hardware (FPGA + SATA storage).
• Technical level: Advanced (assumes familiarity with state-vector simulation, FPGA design, HLS, and storage interfaces).
• Scope: The paper presents Qu-Trefoil, an FPGA-based state-vector quantum circuit simulator built on the Trefoil multi-FPGA storage platform, and reports its gate implementations, system architecture, and measured runtimes for circuits exceeding 43 qubits.

What This Paper Is About

Simulating a quantum circuit with state vectors needs 2^(n+4) bytes of memory for n qubits, so anything beyond roughly 40 qubits has so far been practical only on supercomputers and large GPU clusters. The authors ask whether an FPGA platform with many cheap SATA solid-state disks can hold and process state vectors of that size instead. Their goal is a working simulator that implements a universal gate set on the Trefoil storage subsystem and can simulate circuits over 43 qubits, which the abstract states requires more than 128 TB of memory.

Key Contributions

1. An FPGA-based design that pushes state-vector simulation beyond 40 qubits — described by the authors as the first practical attempt to use FPGAs for state-vector quantum circuit simulation at supercomputer-scale qubit counts.
2. A SATA-oriented data path that exploits burst-mode transfer on the disks to raise throughput against the otherwise slow disk access that dominates runtime.
3. HLS-based implementations of a universal gate set — Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT), T, and 4×4 unitary matrix computation — with each gate specialized into four cases depending on where the target qubit falls (target = 0, within a chunk, across chunks in one disk, across disks).
4. Practical implementation details and an evaluation covering gate performance, chunk size, disk extensibility, and efficiency across SATA generations.

Main Findings

• Achieved scale: The system simulated quantum circuits with over 43 qubits, requiring more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA.
• Per-subsystem capacity: 32 SATA disks of 8 TB each give 256 TB of state-vector storage, enough for up to 43 qubits, with storage access speed up to 24 GBps (4 × 8 ch × 6 Gbps).
• Full-system ceiling: A fully equipped Trefoil (main system plus eight storage subsystems) offers 2 PB total capacity and 192 GBps storage throughput, stated as sufficient for 46-qubit simulation.
• Scaling rule: Adding N SATA disks increases the simulable qubit scale by log2 N, so capacity grows cheaply through disk count rather than through large on-chip memory.
• Storage-interface rationale: SATA was chosen over NVMe because each NVMe SSD needs four serial I/Os versus one for a SATA SSD, allowing more total capacity from limited FPGA I/Os, and because SATA avoids the complex PCIe control that NVMe requires.
• Comparison context: Prior large-scale results cited include Fugaku at 48 qubits, ARCHER2 at 44 qubits with QuEST, NVIDIA's 40 qubits on Selene with Qiskit Aer and 256 DGX A100s, 33 qubits for a DGX H100 GPU server, Intel Quantum Simulator at 42 qubits on 2048 SuperMUC-NG nodes, cuQuantum at 40 qubits with 128 GPUs on an H100 cluster, and mpiQulacs at 36 qubits on 64 A64FX nodes of the Todoroki cluster. Qu-Trefoil's claim is accessibility and cost rather than beating the largest supercomputer runs outright.
• On-chip footprint context: FPGAs with HBM/HBM2 offer only about 4 GB to 32 GB, which runs into memory problems above 35 qubits; the paper notes gate computation itself is not compute-intensive, mostly data interchange or coefficient multiplication, so mid-range DSP resources suffice.
• Not reported in the provided text: The detailed numerical results for the chunk-size sweep, disk-extensibility sweep, and SATA II versus SATA III comparison are described as part of the evaluation but their specific values are not present in the supplied content.

Methodology in Plain English

The simulator keeps the quantum state vector on disk rather than in memory. The state is split into chunks, where one chunk equals 32 sectors and one sector is 512 bytes; because each amplitude is a double-precision complex number of 16 bytes, exactly 32 amplitudes fit in a sector. The FPGA reads a chunk into on-chip buffers, applies the gate's arithmetic, and writes the result back.

The disk side is handled with LiteX and its open-source LiteSATA controller, because Xilinx does not provide open-source disk-controller IP. The authors extended LiteSATA so multiple SATA cores can be accessed at once, a configuration LiteX does not officially support, and they revised initialization to automate link-up detection and hot-swap for multiple cores. LiteSATA is used at SATA II (3.0 Gbps) and SATA III (6.0 Gbps) with 48-bit logical block addressing, with a system clock of 150 MHz or 156.25 MHz depending on the generation.

The gate logic is written in Vitis HLS 2022.2.2.2 rather than Verilog or VHDL, for faster prototyping and easier maintenance. Because a gate's memory-access pattern depends entirely on where the target qubit sits, each gate is compiled into four variants: target equal to 0 (interleaved adjacent amplitudes, handled by a specialized module), target inside a chunk (random access, so full pipelining is impossible and only the compute and write stages are pipelined and unrolled), target spanning two chunks in one disk (two chunks read into separate buffers, two write-backs), and target spanning two disks (two input/output streams with separate user signals). Read and compute are pipelined against each other, and write and compute likewise, using fixed protocol regions in the code to keep HLS scheduling clean.

Operation is straightforward: the user loads a bitstream over JTAG, enters parameters such as qubit scale and target qubit through a Python GUI on a Raspberry Pi 3, the FPGA performs the gate computation writing results across the 32 SATA disks, and results are read back to the Raspberry Pi 3 for visualization.

Why This Matters

The work shows that a storage-attached FPGA can reach qubit counts previously associated with supercomputer runs, at a cost and accessibility level suited to groups without HPC allocations. It also reframes the bottleneck of state-vector simulation as a storage-bandwidth problem rather than a floating-point problem, which is a useful design principle for anyone building simulation hardware.

Real-world applications:

• Debugging and verifying quantum algorithms and circuits at 40-plus qubits without a physical quantum computer or supercomputer time.
• Quantum error correction and phase-estimation studies, which the paper highlights as needing double-precision accuracy because small numerical errors accumulate.
• Benchmarking and cross-checking the behaviour of algorithms such as Grover's algorithm and the quantum approximate optimization algorithm at scales that capture their core characteristics.
• Low-cost, edge-deployable simulation infrastructure for academic and industrial labs, since Trefoil can run autonomously in edge computing environments without a host workstation.

Industry relevance: the design leans on commodity SATA SSDs (Samsung 870 QVO 8 TB) and mid-range FPGA resources, so capacity scales by plugging in more disks rather than by buying accelerator memory. For FPGA and storage vendors, and for cloud or HPC providers looking for cheaper ways to offer large-scale quantum simulation as a service, that is a directly relevant cost argument.

Future Directions

• Close the gap to the full machine: The reported runs use one storage subsystem with one FPGA; demonstrating aggregate multi-subsystem operation toward the stated 46-qubit, 2 PB, 192 GBps configuration is the natural next step.
• Attack the disk bottleneck: The paper identifies slow SATA access as the dominant limitation, so deeper overlap of disk transfer with gate computation, or migration to faster storage interfaces while preserving I/O-count efficiency, is an open engineering question.
• Broaden the gate set: Beyond H, Z, S, CNOT, T, and the 4×4 unitary, adding multi-qubit and parameterized gates would let the system handle a wider range of application circuits.
• Quantify precision and noise trade-offs: Since double precision is defended on accuracy grounds for error-correction and fault-tolerant workloads, systematic study of where reduced precision would suffice — and how much throughput it would buy — remains open.

Target Audience

Researchers and engineers working on quantum circuit simulation, FPGA-based accelerators, and reconfigurable computing, particularly those interested in out-of-core or storage-backed simulation architectures. It also suits HPC and quantum-software practitioners who want a low-cost alternative to supercomputer-scale state-vector simulation, and FPGA/storage architects interested in tightly coupled multi-disk designs. Readers should be comfortable with hardware design flow and state-vector formalism; the paper is not an introductory quantum computing text.

Authors’ abstract

Quantum circuits are fundamental components of quantum computing, and state-vector-based quantum circuit simulation is a widely used technique for tracking qubit behavior throughout circuit evolution. However, simulating a circuit with $n$ qubits requires $2^{n+4}$ bytes of memory, making simulations of more than 40 qubits feasible only on supercomputers. To address this limitation, we propose the Qu-Trefoil, a system designed for large-scale quantum circuit simulations on an FPGA-based platform called Trefoil. Trefoil is a multi-FPGA system connected to eight storage subsystems, each equipped with 32 SATA disks. Qu-Trefoil integrates a suite of HLS-based universal quantum gates, including Clifford gates (Hadamard (H), Pauli-Z (Z), Phase (S), Controlled-NOT (CNOT)), the T gate, and unitary matrix computation, along with HDL-designed modules for system-wide integration. Our extensive evaluation demonstrates the system's robustness and flexibility, covering quantum gate performance, chunk size, disk extensibility, and efficiency across different SATA generations. We successfully simulated quantum circuits with over 43 qubits, which required more than 128 TB of memory, in approximately 3.72 to 13.06 hours on a single storage subsystem equipped with one FPGA. This achievement represents a significant milestone in the advancement of quantum computing simulations. Furthermore, thanks to its unique architecture, Qu-Trefoil is more accessible, flexible, and cost-efficient than other existing simulators for large-scale quantum circuit simulations, making it a viable option for researchers with limited access to supercomputers.