Parallel Circuit Execution for Scalable Quantum Computation

AI summary

Overview

• Research area: Quantum computing systems — specifically multiprogramming quantum computers (MPQC), circuit compilation/mapping, and GPU-accelerated classical simulation.
• Technical level: Intermediate. The core idea is simple, but full engagement requires familiarity with qubit topologies, transpilation, Pauli grouping, and MPI-based HPC execution.
• Scope (1 sentence): The paper presents an error- and topology-aware method for running many independent quantum circuits simultaneously on disjoint regions of a single QPU (and, analogously, across multiple GPUs), and measures the resulting execution-time savings and fidelity costs on IBM's 156-qubit ibm_boston processor and on the NERSC Perlmutter GPU system.

What This Paper Is About

Today's quantum processors have tens to hundreds of physical qubits, yet noise limits reliable execution of arbitrary circuits to fewer than 30 entangled qubits, leaving most of the device idle during any given run. The authors exploit that idle capacity by splitting a large processor into several low-error, disjoint qubit regions so that many independent circuits—such as the measurement circuits produced when a Hamiltonian is broken into commuting Pauli groups—run at the same time instead of one after another. The goal is to reduce billed QPU execution time and GPU simulation time without destroying result quality.

Key Contributions

1. An error- and topology-aware partition mapper. A lightweight greedy algorithm scores candidate qubit regions by average two-qubit gate error, diameter, and internal edge count, then selects disjoint partitions while enforcing a minimum spacing gap. This fills a gap the authors identify in Qiskit's ParallelExperiment, which composes sub-experiments onto disjoint qubits but provides no built-in error-aware mechanism for deciding which qubits to assign.
2. A practical hardware execution path. The method handles mixed-width circuit batches through a two-phase partition allocation, uses array batching so that an entire workload is submitted as a single job, and adds a try/fallback transpilation strategy (optimization level 1, falling back to pre-transpilation onto a restricted coupling map at optimization level 0) to keep routed circuits inside their assigned partitions.
3. Two new runtime-selectable execution modes in the QED-C benchmark suite. A --parallel (-pm) mode distributes independent circuits across MPI groups of GPUs, and a --gpus_per_circuit (-gpc) hybrid mode combines circuit-level parallelism with statevector distribution across multiple GPUs, implemented using MPI subcommunicators backported from CUDA-Q 0.15 to CUDA-Q 0.13.
4. Dual validation on hardware and simulation. The same workload structure is evaluated on a real 156-qubit QPU and on GPU simulation that delivers 100% fidelity, establishing both a practical cost/quality tradeoff on today's devices and a ceiling for what future hardware could approach.

Main Findings

Execution-time savings on real hardware. On IBM's 156-qubit ibm_boston processor, parallel execution reduced billed execution time by 3.5–5.5× compared with standard sequential execution while retaining 83–92% of the sequential fidelity.

Gains vary by workload. Average QPU speedups were 3.52× across standard QED-C benchmarks and 5.20× across observable-estimation workloads. Per-benchmark averages were 3.64× (QFT), 3.58× (Bernstein–Vazirani), 3.33× (TFIM Hamiltonian simulation), 4.44× (TFIM observable estimation), 8.68× (Bose-Hubbard), and 2.48× (H2).

A representative hardware result. For Bose-Hubbard observable estimation at 8 qubits, parallel execution gave a 2.8× reduction in billed quantum execution time while retaining 89.5% of sequential fidelity.

Partitioning can occasionally help accuracy. In some cases the parallel result was closer to the exact value than the sequential one, consistent with the error-aware mapper steering circuits toward favorable regions of the processor.

GPU speedup tracks the number of independent groups. On 16 NVIDIA A100 GPUs on Perlmutter, the authors measured 1.9× for TFIM (2 commuting groups), 8.2× for Bose-Hubbard (9 groups), and 13.8× for H2 (1,251 groups at 20 qubits), the last representing 86% of the theoretical maximum. Wall-clock times for those three cases were 1.70 s → 0.90 s, 53.54 s → 6.50 s, and 283.81 s → 20.51 s respectively.

Averaged GPU results are more modest than the peak. Across all evaluated problem sizes, circuit-level parallelism averaged 1.52× on standard QED-C benchmarks (1.69× on 4 GPUs, 1.16× on 8, 1.72× on 16) and 3.56× on observable estimation (2.02×, 2.86×, 5.79×). The H2 workload averaged 5.97× overall and 9.96× at 16 GPUs.

Scaling is non-monotonic on GPUs. Performance can drop from 4 to 8 GPUs when execution crosses a single NVLink-connected node and pays inter-node communication cost—Hidden Shift averaged 0.76× at 8 GPUs—before 16 GPUs offset that overhead for larger problems.

Group count, not qubit count, limits parallel speedup. TFIM with only two commuting groups improved little beyond two GPUs, whereas H2 with up to 1,251 groups had enough independent circuits to occupy all 16.

Fidelity loss has a clear mechanism. Partition-constrained placement and routing add overhead, and deeper circuits degrade more; the pre-transpile fallback guarantees containment but costs 10–25% fidelity due to extra SWAP insertions in the restricted topology.

Sampling is not systematically biased by distribution. Shot-based expectation values from the GPU runs remained closely aligned across 1, 4, 8, and 16 GPUs.

Hardware and simulation settings. GPU experiments used CUDA-Q 0.13.0 with mpi4py and Python 3.12 on Perlmutter (four NVIDIA A100 40 GB GPUs per node, interconnected by HPE Slingshot 11; 16 GPUs spanned 4 nodes). Hardware experiments used Qiskit 2.5, qiskit-ibm-runtime 0.48.0, and qiskit-experiments 0.14.0. HamLib experiments used K = 1 Trotter step, t = 0.1, and 10,000 shots per circuit.

Methodology in Plain English

The workflow starts with a Hamiltonian, which is decomposed into commuting Pauli groups; each group becomes an independent measurement circuit. Because these circuits share no state, they are natural candidates for simultaneous execution.

For hardware, the authors first look for "parking spots" on the chip. Starting from each qubit, they grow a connected cluster of the required circuit width by repeatedly preferring the node with the most connections to the existing cluster, which favors compact regions over long chains. Each candidate is ranked first by its average two-qubit gate error from backend calibration data, then by its diameter (shorter is better for routing), then by how many internal edges it offers the transpiler. Partitions are taken in score order, with a default 2-hop gap between them to reduce crosstalk; if too few fit, the gap is relaxed 2 → 1 → 0, and any partition whose average two-qubit error exceeds a default threshold of 0.02 is rejected outright.

Circuits are then dealt round-robin into ⌈N/P⌉ composite circuits per partition, and Qiskit's ParallelExperiment array support submits the entire batch as a single job, removing repeated queue waits. Mixed-width batches are handled in two phases: one partition per unique width starting from the largest, then extra partitions for widths already represented.

Transpilation is the tricky part. For shallow circuits the transpiler respects partition boundaries; for deeper ones its router may insert SWAPs that escape the partition. The authors first try full optimization (level 1) and, if the boundary is violated, fall back to pre-transpiling each circuit onto a coupling map built only from that partition's internal edges, then run at optimization level 0.

For GPUs, total MPI ranks are split into G = T/P independent groups via subcommunicators, with P = 1 giving pure circuit-level parallelism and P > 1 giving hybrid circuit-plus-statevector parallelism. The theoretical maximum speedup is min(G, C) for C independent circuits. GPU simulation runs the same shot-based sampling model as hardware, so it doubles as a 100%-fidelity reference for validating the hardware results.

Why This Matters

The paper reframes idle qubits as a usable resource rather than a symptom of the pre-fault-tolerant era: when reliable circuits are capped at roughly 10–15 entangled qubits on superconducting devices (about 30 on trapped-ion) while devices offer 50–150 or more, multiplexing independent circuits converts qubit count into throughput. It also provides a concrete, reusable implementation inside a community benchmark suite, so the effect can be measured consistently rather than anecdotally.

Real-world applications:

• Quantum chemistry: the H2 electronic-structure workload, with 54–1,251 commuting groups, is exactly the shape where parallel execution pays off, and the same structure applies to larger molecular Hamiltonians in drug and catalyst discovery pipelines.
• Materials and condensed-matter simulation: TFIM and Bose-Hubbard observable estimation map directly onto lattice and many-body model studies on near-term hardware.
• Variational and hybrid algorithms: VQE and Trotterized Hamiltonian simulation both require many independent measurement circuits, which this method schedules concurrently.
• HPC-integrated quantum workflows: the GPU path shows how supercomputer users can trade qubit capacity for circuit throughput when simulating quantum workloads at scale.

Industry relevance: cloud quantum access is billed by execution time, so a 3.5–5.5× reduction in billed time on real hardware has a direct cost implication for service providers and users. The work also connects vendor ecosystems—IBM Quantum hardware, NVIDIA CUDA-Q, and the QED-C benchmark standards—and was authored across a national laboratory, a hardware/software vendor, a university, and a standards committee.

Future Directions

• Scaling with device quality and qubit count. The authors frame the GPU results as a ceiling that hardware should approach as more, better partitions become available; quantifying that trajectory is left open.
• Closing the fidelity gap. The 83–92% fidelity retention and the 10–25% penalty from the pre-transpile fallback point to better partition-constrained routing and crosstalk-aware compilation as clear targets.
• Beyond IBM devices. The partition finder needs only a coupling map and calibration data and is not IBM-specific, but experiments were performed only on IBM devices—testing on other modalities is an open step.
• Reducing setup overhead. Some partitioned-execution setup can be precomputed and reused across runs, particularly for workloads that repeat with different runtime parameters; how far that amortization can go is not resolved here.
• Broader workload coverage. The results cover a limited set of QED-C programs and three HamLib Hamiltonians, leaving generalization to other algorithm families and Hamiltonians to be established.

Target Audience

Quantum software and compiler engineers building multi-programming or partitioning tools; researchers running Hamiltonian simulation and observable-estimation workloads on near-term hardware; HPC specialists distributing quantum circuit workloads across GPU clusters with CUDA-Q and MPI; and quantum benchmarking teams or cloud providers who care about billed execution time and throughput rather than raw qubit count. Readers without a quantum background will follow the high-level argument but will need supplementary reading on qubit topology, transpilation, and Pauli grouping.

Authors’ abstract

Today's quantum processors have tens to hundreds of physical qubits, but reliable execution of arbitrary circuits remains limited to fewer than 30 entangled qubits across hardware modalities. Building upon prior work, we introduce an error- and topology-aware method for mapping multiple independent circuits onto disjoint regions of a single large-scale QPU for parallel circuit execution. For applications with many similarly sized circuits, such as observable estimation for Hamiltonian simulation, this approach can reduce billed QPU execution time, with ideal speedup proportional to the number of usable partitions. We demonstrate the approach on IBM's 156-qubit ibm_boston processor using standard QED-C benchmark and Hamiltonian-based observable-estimation workloads. Compared with standard sequential execution, parallel execution reduces billed execution time by 3.5-5.5x while retaining 83-92% of the sequential fidelity. We further evaluate the scaling of parallel circuit execution using GPU-accelerated classical simulation, distributing measurement circuits across GPUs via MPI. Using CUDA-Q on the NERSC Perlmutter system, we achieve up to 13.8x speedup on 16 GPUs (86% parallel efficiency) for an H2 electronic-structure simulation, with scaling evaluated across multiple Hamiltonians and circuit counts. These results provide an indication of the performance ceiling that parallel execution on future quantum hardware may eventually approach. Both execution modes are implemented as a runtime option within the QED-C Application-Oriented Benchmark suite. Together, the results show that circuit-level parallelism can reduce execution cost on current quantum hardware and simulation time on GPU clusters, with the potential for greater benefits as device quality and qubit counts increase.