NAQsim: Full-Stack Architecture Simulation Framework for Fast and Space-Efficient Neutral Atom Quantum Computing

AI summary

Overview

Research area: Quantum computer architecture and design automation, specifically full-stack modeling and co-design of fault-tolerant quantum computers (FTQC) built on neutral-atom hardware using the transversal surface code.

Technical level: Advanced. The paper assumes familiarity with surface-code error correction, transversal gates, Rydberg blockade, acousto-optic deflector (AOD) shuttling, and microarchitectural simulation.

Scope (one sentence): The paper introduces NAQsim, an open-source three-stage (compile, execute, estimate) simulation framework for neutral-atom FTQC, uses it to expose patch rotation as a dominant bottleneck (55.3%–77.6% of execution time), and co-designs a "near-rotation-free" architecture, D3-ROT, that delivers an average 2.27× speedup (up to 2.57×) for a 22.4% average footprint overhead.

Note: the supplied paper content ends partway into Section V, so the detailed rotation-implementation trade-off study (Section V-C) and the space-time comparison against lattice surgery (Section VI) are not available for summary.

What This Paper Is About

Neutral-atom quantum computers have recently gained fast, shuttling-free error syndrome measurement thanks to selective Rydberg gates and selective imaging, but logical operations such as transversal CX and transversal H still require physically moving atoms with AODs, which takes hundreds of microseconds to milliseconds and leaves these machines roughly 58× slower than superconducting lattice-surgery architectures in the authors' analysis. Architects lack any tool that can model the interaction among compiler scheduling, laser control hardware, and qubit-plane geometry for this platform, so the paper builds one (NAQsim) and then uses it to find and fix a previously overlooked performance bottleneck, logical-qubit patch rotation.

Key Contributions

1. First full-stack neutral-atom FTQC simulation framework. NAQsim models compilation, laser-level execution, and error/overhead estimation for transversal surface-code architectures, and captures neutral-atom-specific features that prior superconducting- or lattice-surgery-focused tools (e.g., Quration) do not: atom shuttling, AOD route conflicts, laser pattern-change costs, AOD–SLM transfer noise, and logical-qubit patch overlap.
2. A micro-operation (µop) abstraction plus detailed AOD pipeline simulation. Logical instructions are decomposed into laser-wise µops, scheduled with dependency and "route conflict" analysis, and simulated with accurate latency models, including the restricted set of allowed movement directions on a regular SLM lattice.
3. Full-stack co-optimization of a previously overlooked bottleneck. The authors quantify patch rotation at 55.3%–77.6% of total execution time and propose three "D"-prefixed fixes: direct rotation with SLM laser toggling (control hardware), dedicated rotation patches (qubit plane), and distribution of rotations (compiler).
4. D3-ROT architecture and open-source release. The combined design yields a near-rotation-free architecture with an average 2.27× speedup, up to 2.57×, for a modest 22.4% average footprint overhead; the tool is released at github.com/naqsim/naqsim.

Main Findings

• The logical-operation gap is large: state-of-the-art neutral-atom architectures still show a performance gap of 58× relative to superconducting qubit platforms in the authors' analysis, because AOD-based logical operations cost a few hundred microseconds to several milliseconds even though shuttling-free ESM has been reduced substantially.
• Patch rotation dominates runtime: across the evaluated practical FTQC workloads, patch rotation accounts for 55.3%–77.6% of total execution time. Rotation is required because a transversal logical H swaps the rotated surface code's boundary orientation, so the atom array must be physically rotated by π/2 to restore alignment for later transversal CX gates.
• D3-ROT results: an average speedup of 2.27× and up to 2.57×, with an average footprint overhead of 22.4%; the abstract attributes the 2.27× to "this single bottleneck alone."
• Benchmark suite: eight workloads across four algorithm classes, with logical-qubit counts of 167 (2D Heisenberg), 95 (2D Fermi–Hubbard), 41 (Jellium), 27 (H4), 64 (adder), 29 (QFT), 64 (1D Ising), and 64 (2D Ising). Transversal code distances chosen for 99.9% program success were d = 23, 23, 23, 17, 13, 15, 15, 17; lattice-surgery comparison distances were d = 27, 27, 27, 21, 17, 19, 19, 21. Transversal physical-qubit counts ranged from 13,470 (QFT) to 177,576 (Heisenberg), versus 93,730 to 1,014,072 for lattice surgery.
• Rotation count versus gate mix: the QPE workloads' repetitions were 48,067 (Hei), 56,549 (FH), 38,075 (Jellium), and 975 (H4), with CX/H/S/T counts reported per workload in the paper's Table II; QFT has the largest H count at 48,737 and T count at 58,240.
• Validated logical error rate models: NAQsim fits analytic LER models (Eqs. 2 and 3) as functions of code distance and number of AOD pick/drop transfers per layer, trained on d = 3, …, 13 and checked against Stim/PyMatching simulations at d = 23 (error parameters scaled 11× for 1-LQ and 7× for 2-LQ operations to make the measurement feasible). Agreement gave RMSEs in log10 LER of 0.162 (1-LQ) and 0.097 (2-LQ).
• Route conflicts matter for accuracy: naive "wait until the other move finishes" modeling overestimates execution time, so the framework computes entry/exit intervals for every patch touched and derives the minimum delay needed to avoid atom collisions.
• Space accounting: physical qubit count is computed as (# LQ patches) × (2d² − 1), with each minimal patch occupying (2d+2)² SLM traps; footprint area is reported separately so that ideas trading area for speed are not hidden.

Methodology in Plain English

The framework takes four user inputs: a quantum program (OpenQASM, Clifford+T), a logical instruction set (INIT_X/INIT_Z, Pauli gates, TR_H_ROT, TR_CX, M_X/M_Z/M_FB, and resource-state requests REQ_Y/REQ_TY), a qubit-plane layout of logical-qubit patches plus resource-state ports, and a laser/hardware configuration with latencies and error rates.

It then runs three stages. Compilation translates gates into a dependency graph, schedules them into instruction layers (ASAP for most instructions, ALAP for resource requests to avoid deadlock, Pauli gates tracked in a Pauli frame), and places logical qubits on the plane via simulated annealing adapted from a prior NISQ compiler. Execution turns each instruction into laser-wise micro-operations (H with a Raman laser, measurement with an imaging laser, CZ with a Rydberg laser, MOV and ROT with AOD lasers, plus one ESM round per layer for all live logical qubits), then runs a processor-pipeline-style decode/dependency-check/issue/execute loop. Move generation for transversal CX is posed as a minimum-weight bipartite matching between CX instructions and candidate patches, with a cube-root-based cost function that reflects the restricted one-step and two-step movement routes and STA-trajectory shuttle latency. Estimation sums the execution trace into total runtime, counts physical qubits and footprint area, and multiplies per-layer logical error rates over all live logical qubits to give a program success rate.

For the architectural study, the authors profile the execution traces to find where time goes, identify patch rotation as the dominant cost, propose one fix in each of the three stacks (hardware, qubit plane, compiler), and combine them into D3-ROT. The evaluation assumes state-of-the-art selective lasers with a deliberately generous number of AODs (a limited-AOD sensitivity analysis is promised in Section VI-C), CZ/measurement/reset/AOD–SLM transfer error rates of 0.1%, single-qubit gate error of 0.01%, and T2 = 10 s.

Why This Matters

Research impact. The paper reframes the neutral-atom performance problem: fast ESM alone is insufficient, and the community's attention should shift to logical-operation implementation, especially movement and rotation. It also supplies the missing measurement instrument—an open-source, full-stack, neutral-atom-aware evaluator—for a design space where compiler, laser control, and qubit-plane geometry are tightly coupled and where prior tools (built for superconducting lattice surgery) are structurally inadequate. The rotation finding is a concrete demonstration that full-stack visibility surfaces bottlenecks invisible to single-layer analysis.

Real-world applications (as framed by the paper's benchmarks):

• Quantum chemistry and materials: qubitization-based QPE for the 2D Heisenberg model, 2D Fermi–Hubbard model, Jellium, and the H4 molecule, aimed at ground-state energy estimation in early-FTQC applications.
• Quantum dynamics simulation: 5-Trotter-step 1D and 2D Ising time-evolution circuits.
• Quantum arithmetic and cryptographically relevant primitives: reversible adders used in modular arithmetic, period finding, and arithmetic oracles.
• Spectral and subroutine workloads: the quantum Fourier transform, a standard subroutine in phase estimation, period finding, and arithmetic.

Industry relevance. Hardware startups and national labs choosing between neutral-atom and superconducting roadmaps need quantitative time/space/error trade-offs before committing to a qubit-plane geometry or laser architecture; a tool that models AOD channel counts, SLM pattern-change costs (1000 μs), and pick/drop overhead (40 μs) lets them budget laser resources and footprint rather than guess. Because the framework is open source, it can become shared infrastructure for architecture benchmarking.

Future Directions

• Beyond the transversal surface code. The authors explicitly state that their results point to a broader space of full-stack optimizations "for transversal surface-code architectures and beyond," inviting extension to other codes and FTQC protocols with greater modeling complexity than lattice surgery.
• Limited-laser and resource-constrained regimes. The main evaluation intentionally assumes a sufficient number of AODs to expose bottlenecks that more lasers cannot fix; a sensitivity analysis under limited AOD resources is promised (Section VI-C) and opens the question of how D3-ROT behaves when laser channels are scarce.
• Richer rotation implementations. Section V-C is described as exploring trade-offs among patch-rotation implementations depending on AOD type and qubit-plane configuration (single versus multiple atom movements), leaving room to optimize rotation further or eliminate it entirely.
• Integration with distillation and resource-state supply. Resource states and ports are deliberately abstracted behind REQ instructions to decouple distillation design from compilation; connecting real distillation protocols and port counts to the architecture model is a natural next step.
• Broader error and hardware modeling. The logical error model is fitted and validated at specific distances and transfer counts, and the paper's error budget uses fixed 0.1%/0.01% physical rates; extending validation across wider parameter ranges and including crosstalk or leakage would strengthen architectural conclusions.

Target Audience

Quantum architecture and computer-aided-design researchers; neutral-atom experimentalists and hardware engineers deciding on laser systems, AOD counts, and trap geometry; FTQC resource-estimation and compilation researchers working on transversal-gate protocols; and graduate students or industry architects who need a quantitative, full-stack view of where neutral-atom fault-tolerant machines lose time and area compared with superconducting alternatives. Readers without surface-code and shuttling background will find the framing accessible but the modeling detail demanding.

Authors’ abstract

Technological advances in neutral-atom platforms have opened a new path toward designing efficient protocols for fault-tolerant quantum computing (FTQC). However, each physical operation is still orders of magnitude slower than on other platforms, such as superconducting qubits. Therefore, architects must identify fast and efficient FTQC architectures, which require reliable modeling tools to explore various design choices across the software, classical hardware, and quantum device stacks of neutral-atom platforms. In this paper, we propose NAQsim, an open-source simulation framework for neutral-atom FTQC architectures based on transversal gates. As its key feature, NAQsim enables detailed full-stack architecture evaluation that opens opportunities to explore previously overlooked performance bottlenecks. As a first use case for NAQsim, we identify one such bottleneck, patch rotations, perform full-stack co-optimization, and finally derive a near-rotation-free architecture (D3-ROT). For practical FTQC benchmark workloads, D3-ROT achieves a 2.27x speedup from this single bottleneck alone, with minimal footprint overhead. These results point to a much broader space of full-stack optimizations that NAQsim makes accessible for transversal surface-code architectures and beyond.