Modular Neural Decoder for Surface Code Memory and Logic on Superconducting Processors

AI summary

Overview

Research area: Quantum error correction (QEC) for superconducting processors, combining surface-code experiments with machine-learning decoders.

Technical level: Intermediate — assumes familiarity with surface codes, stabilizer measurements, and basic neural network concepts, but the paper is written in an unusually accessible experimental style.

Scope: The paper presents a modular graph-neural-network + recurrent decoder that is pretrained in simulation and fine-tuned to hardware, and tests it on IBM and Google superconducting devices across memory, stability, and lattice-surgery (ZZ-merge) experiments.

What This Paper Is About

A quantum computer's logical qubits only stay alive if a classical "decoder" can correctly infer, from noisy stabilizer measurements, whether an error has flipped the encoded information. Neural decoders have recently beaten classical algorithms on single memory experiments, but it has been unclear whether one architecture can be reused across different chips, different noise levels, and different kinds of logical operations without being rebuilt each time. This paper builds such a portable decoder and tests it on real superconducting hardware in three distinct experimental settings: memory, stability, and a lattice-surgery ZZ merge.

Key Contributions

1. A modular, renormalization-inspired decoder architecture. A single shared d=3 graph-neural-network encoder processes 3×3×2 space-time blocks of detection events; small convolutional layers aggregate tile embeddings into larger code distances, and a GRU integrates over time. Parameter count is nearly independent of distance (≈1.6M for standalone d=3, ≈1.9M at d=5, ≈2.3M at d=7 and d=9).

2. A reusable three-stage training pipeline (synthetic pretraining, calibrated error-model fine-tuning, then real-data fine-tuning) applied identically across two hardware platforms and three experiment types.

3. Extension beyond memory decoding on the same IBM device: decoding of an X-type stability experiment (the structural proxy for the lattice-surgery merge step), including a new protocol that sweeps effective measurement error via a variable pre-readout R_X(α) rotation.

4. Decoding of an actual ZZ-merge lattice-surgery experiment between two d=3 surface-code patches on real hardware, using a 1×3 convolutional aggregation over three d=3 tiles (patch 1, bridge, patch 2).

Main Findings

• IBM memory beats MWPM at d=3 and d=5. On ibm_berlin (IBM Nighthawk r1), fitted error per round: d=3 (q36) 1.47% for GNN-RNN versus 2.79% for MWPM; d=3 (q85) 1.26% versus 2.60%; d=5 (q85) 2.48% versus 3.79%. At d=5 both decoders approach the random-guessing ceiling at t=50, where the neural decoder's advantage disappears.

• No below-threshold suppression on this IBM device. Growing the q85 core from d=3 to d=5 nearly doubles detection-event density (16% to 28%); the GNN-RNN error per round rises from 1.26% to 2.48%, and MWPM's rises from 2.60% to 3.79% — the opposite of the trend seen on Google hardware.

• Google hardware: close to AlphaQubit at d=3, gap grows with distance. Averaged over patches in the Z basis: ε₃ ≈ 0.638%, ε₅ ≈ 0.330%, ε₇ ≈ 0.179% (wide model), with ε₃/ε₅ ≈ 1.94, ε₅/ε₇ ≈ 1.84, and Λ ≈ 1.9. MWPM on the same calibrated p_ij models gives ε₃ ≈ 1.35%, ε₅ ≈ 0.849%, ε₇ ≈ 0.562%, Λ ≈ 1.56. AlphaQubit reports ε₃ = 0.616%, ε₅ = 0.276%, ε₇ = 0.130%; the decoder is within 4% at d=3, but the gap widens to 20% at d=5 and 38% at d=7.

• Recurrent capacity explains part of the remaining gap. The default d=7 model reaches ε₇ ≈ 0.215% (65% above AlphaQubit); widening the GRU hidden size from 256 to 1024 (≈30M parameters) lowers this to 0.179%, closing about 40% of the gap without changing the spatial modules.

• Stability experiment: advantage grows with duration. On the d=3 X-type stability circuit, the GNN-RNN beats MWPM at every duration tested — a 15% error reduction at t=5, growing to 45% at t=100. Exponential fits give Λ_t ≈ 1.09 for the GNN-RNN versus 1.07 for MWPM per four rounds. Here the number of rounds plays the role that code distance plays in a memory experiment: p_L decreases with t.

• A single decoder handles a whole noise sweep. Sweeping R_X(α) on every measure qubit (α ∈ {0.15, …, 1.0} rad, at t=20 and t=100, 5×10⁴ shots per point, 17 (t, α) settings combined) produces a monotonic rise in p_L with α, with the t=100 curve below t=20 at every angle. One decoder fine-tuned jointly across all settings matches or beats per-setting-calibrated MWPM, whereas MWPM must re-derive edge weights for each setting.

• ZZ-merge lattice surgery decoded on hardware. With a 1–3–1 round schedule on ibm_berlin (10⁵ shots), held-out test set n=10,002: correction accuracy on the Bell-pair correlation reaches 58.2% for the GNN-RNN, versus 56.2% for MWPM and 54.2% uncorrected. Both decoders remain far from the ideal histogram, attributed to the device's high native noise rather than a decoder limitation.

• Modest compute footprint. Every model was trained on a single NVIDIA GH200 GPU, from a few GPU-hours for fine-tuning up to a few GPU-days for the largest simulated-circuit models, with real-data decoding demonstrated up to d=7 and simulated up to d=9.

Methodology in Plain English

The surface code spreads one logical qubit over many physical qubits and repeatedly measures local stabilizers; when a measurement differs from the previous round, that signals a "detection event." The decoder's job is to look at the pattern of detection events and guess whether the logical bit flipped.

The authors' decoder works in small chunks. Detection events within a two-round sliding window are turned into a graph — each event a node, connected to all others with weights that decay with space-time distance — and a graph neural network compresses that graph into one vector. A recurrent network (a GRU) then reads the sequence of these vectors over time and a final linear layer outputs the flip probability. Because the spatial network only ever looks at one window and the recurrent unit carries the temporal context, a model trained on 50 rounds generalizes to 1000.

To go to larger code distances, the authors reuse the same d=3 encoder on overlapping tiles (four tiles at d=5, nested further at d=9, nine tiles on a 3×3 grid at d=7, which doesn't fit the four-tile recursion) and combine the tile vectors with a small convolution. Each added level costs only about 0.3 million parameters (0.66 million for the 3×3 case at d=7). The experiment type enters only through the binary label the head is trained on and the tiling layout — the input graph construction is identical for memory, stability, and merge circuits.

Training happens in three stages: (1) synthetic Stim circuits with depolarizing noise p ∈ {0.001, …, 0.005} or a superconducting-inspired SI1000 model scaled to the device's detection-event density; (2) fine-tuning on synthetic samples from a detector error model fitted from the device's own correlation probabilities up to fourth order; (3) fine-tuning on the recorded hardware detection events, split 80/10/10 into train, validation, and a held-out test set from which all reported numbers come. MWPM baselines (PyMatching) run on the same Stage-2 p_ij models, so the matching decoder gets device-informed edge weights.

A hardware-specific detail: because mid-circuit reset is slow on ibm_berlin, measure qubits are measured but never reset, and the standard per-round detection event is recovered by comparing outcomes two rounds apart. The stability experiment adds a variable R_X(α) rotation before readout, which realizes an extra measurement flip of probability sin²(α/2) and lets the authors tune the effective measurement error rate on demand.

Why This Matters

Impact on research. The paper reframes neural decoding as a portability problem rather than a single-benchmark accuracy contest. It shows that a small, single-GPU model with a shared local encoder can be moved across vendors, noise regimes, and qualitatively different observables with only lightweight aggregation changes, and it traces the residual accuracy gap to AlphaQubit at large distance to a concrete architectural cause (a fixed-size recurrent state compressing each window into one 256-dimensional vector, so per-stabilizer memory falls as 1/d², versus AlphaQubit's per-stabilizer recurrent state). The stability experiment as a tunable-noise testbed is a reusable methodological contribution beyond this specific decoder.

Real-world applications (as motivated by the paper's framing):

• Fault-tolerant quantum computing on superconducting hardware, where the decoder must keep pace with syndrome measurement rates around 1 μs.
• Rapid benchmarking and bring-up of new quantum processors: one pipeline and a shared pretrained model can be fine-tuned per device instead of re-engineering a decoder from scratch.
• Characterizing devices under deliberately varied noise, using the R_X(α) sweep to probe decoder robustness rather than being limited to a device's fixed native noise.
• Validating lattice-surgery primitives — the building blocks of logical gates such as CNOT — with machine-learned decoding rather than matching alone.

Industry relevance. The work directly engages with industrial results from IBM (Nighthawk r1 / ibm_berlin) and Google (the 105-qubit below-threshold dataset), and benchmarks against AlphaQubit. The claim that every model fits on a single GPU with a few million parameters, plus public code and trained models, lowers the barrier for groups without large-scale decoder infrastructure.

Future Directions

• Closing the large-distance gap. The capacity experiment attributes roughly 40% of the d=7 gap to GRU width alone; architectures that retain per-stabilizer recurrent state while keeping the modular, distance-independent parameter count are the obvious next step.
• Latency and real-time operation. The paper motivates decoding at the ~1 μs syndrome rate, but end-to-end latency or throughput numbers for this decoder are not reported; demonstrating real-time operation, as has been done for scaled AlphaQubit, remains open.
• Scaling to larger codes and more logical operations. Decoding is demonstrated on real data up to d=7 and simulated up to d=9; extending the modular tiling to larger distances and to more lattice-surgery operations (beyond the single ZZ merge) is a natural continuation.
• Multi-head decoding. The authors note that a decoder with several output heads could predict all k independent checks of a given experiment simultaneously, rather than the single combined check used here; the other initialization/readout combinations enumerated in Table 1 remain untested on hardware.

Target Audience

Quantum-computing experimentalists working on superconducting surface codes and hardware error-correction demonstrations; machine-learning researchers interested in architectures for structured, sparse space-time data; and quantum-software engineers building decoding stacks who want a small, portable, openly released model that can be fine-tuned to a new device with modest compute. Readers without background in stabilizer measurements or neural sequence models will find the QEC background section helpful but should expect a moderate learning curve.

Note: the provided content is truncated mid-sentence in the Discussion section, so the paper's full discussion and conclusion are not available here; any claims from those portions are not reported in this summary.

Authors’ abstract

Neural decoders for quantum error correction have achieved high accuracy on surface code memory experiments, but practical fault-tolerant computation requires decoders that transfer across devices, noise conditions, and logical operations. We introduce a modular graph-recurrent decoder designed for this setting. Built from reusable local syndrome encoders, it is pretrained in simulation and fine-tuned to hardware using a common pipeline, with only lightweight spatial aggregation adapted between experiments. The decoder performs competitively on conventional memory benchmarks, outperforming minimum-weight perfect matching (MWPM) at distances 3 and 5 on an IBM Nighthawk-generation processor and closely approaching AlphaQubit on Google's below-threshold hardware data. We then test the framework in two settings beyond memory decoding on the same IBM device. First, in an $X$-type stability experiment, we continuously tune the effective measurement error rate using a variable pre-readout rotation and train a single decoder jointly across the resulting noise range. It matches or outperforms MWPM across the sweep without requiring a separately calibrated decoder for each setting. Second, we decode a $ZZ$-merge lattice-surgery experiment between two distance-3 surface-code patches, improving the decoded correlation between the merge outcome and the final $ZZ$ parity relative to MWPM on real hardware. Together, these experiments demonstrate neural decoding that is portable not only across hardware, but also across qualitatively different surface code observables and logical operations, using models trainable on single-GPU academic resources.