Low loss superconducting resonators enabled by aluminum microstructural engineering and dielectric trimming

AI summary

Overview

• Research area: Superconducting quantum device fabrication — specifically materials engineering of aluminum thin films and silicon dielectric edges for low-loss microwave coplanar waveguide (CPW) resonators.
• Technical level: Intermediate (requires some familiarity with cryogenic microwave measurements, quality factors, and thin-film fabrication).
• Scope: A fabrication-focused study showing that aluminum grain-boundary density controls non-TLS loss and silicon edge/bottom roughness controls TLS loss, with both mitigated to raise the single-photon internal quality factor from 6 × 10⁴ to 2.3 × 10⁶.

What This Paper Is About

Superconducting qubits and the microwave resonators used to read them lose energy to material imperfections, which caps coherence times and quality factors. Most work targets interface losses, but the link between a superconductor's microstructure (grain size) and loss, and between the smoothness of the etched silicon edge and loss, has been poorly understood. This paper isolates those two variables, engineers them deliberately, and shows which loss channel each one controls.

Key Contributions

1. Grain-size engineering of aluminum: Depositing 200 nm Al films at substrate temperatures of RT, 100 °C, 200 °C, and 300 °C increases the AFM-measured average grain size from approximately 100 nm to 200, 380, and 570 nm respectively, reducing grain-boundary density.
2. Direct evidence that grain-boundary loss is non-TLS: Cross-sectional STEM/EDS at 20 nm spatial resolution shows the metal–substrate interface and grain boundaries are oxide-free, with oxidation confined to the metal–air interface — so grain-boundary loss is non-TLS in nature, confirmed by power-dependent loss decomposition.
3. "Tropic" two-step dielectric trimming: An SF₆ isotropic undercut etch followed by a CHF₃ smoothing step preserves the undercut geometry while removing the redeposition roughness that SF₆ alone leaves behind; two variants (Rtropic at 60 mTorr, Stropic at 5 mTorr SF₆ pressure) differ only in sidewall roughness.
4. A 40-fold quality-factor improvement from 6 × 10⁴ to 2.3 × 10⁶ (described in the abstract as a two-orders-of-magnitude improvement) by combining 300 °C aluminum deposition with the Stropic etch, plus a demonstration that etch depth shifts resonant frequency and can serve as post-fabrication frequency trimming.

Main Findings

• Grain size vs. temperature: Average Al grain size rises from approximately 100 nm (room temperature) to 200 nm (100 °C), 380 nm (200 °C), and 570 nm (300 °C), with progressively fewer grain boundaries.
• No oxide at grain boundaries: EDS line profiles and HAADF imaging of the 300 °C film show an oxide-free metal–substrate interface and film bulk; an oxide signal appears only at the metal–air interface.
• Metal-only improvement: Mean single-photon internal quality factor Q_i increases from 4 × 10⁴ at room temperature to 4.2 × 10⁵ at 300 °C before any dielectric trimming.
• Roughness is not the limiter for the metal: Peak-to-peak Al surface roughness rises from 23 nm at room temperature to roughly 165 nm at 300 °C (about 80% of the 200 nm film thickness), and average roughness from 2 nm to 22 nm — yet Q_i improves, indicating grain-boundary density dominates non-TLS loss over surface roughness.
• Etching matters independently: Applying the trimming profiles to the 300 °C film raises Q_i to 2.3 × 10⁶ in the Stropic condition, a factor of 40 over the unetched baseline.
• Sidewall smoothness roughly doubles Q_i: Rtropic and Stropic have comparable etch depths (3.9 µm versus 4.2 µm), so the Q_i difference between them is attributed to sidewall smoothing; an Stropic device etched to 3 µm rather than 4.2 µm gave consistent performance, ruling out etch depth as the cause.
• Loss decomposition separates the mechanisms: Fitting with 1/Q_i = 1/Q_TLS + 1/Q_non-TLS, where 1/Q_non-TLS = 1/Q_hp and 1/Q_TLS = 1/Q_lp − 1/Q_hp, shows increasing deposition temperature reduces non-TLS loss while TLS loss stays essentially constant, whereas etch profile changes reduce TLS loss.
• Operation at high frequency: Because deeper etching lowers the effective permittivity and pushes frequency up, the best devices operate at 6.5–8.1 GHz, above typical quality-factor studies, where TLS defect density is higher — the paper argues this makes the result more demanding.
• Etch depth tunes frequency: Resonant frequency is plotted against profilometry-measured etch depth for the four profiles, establishing local deep etching under a protective resist as a post-fabrication frequency-tuning route without changing resonator design or length.

Methodology in Plain English

The team made four chips from high-resistivity silicon (ρ ≥ 10 kΩ·cm), cleaning in piranha for 10 min and dipping in BOE 7:1 for 5 min to strip native oxide. They loaded the wafers into an electron-beam evaporator, pumped to below 8 × 10⁻⁸ mbar, and deposited 200 nm of aluminum at 10 Å/s — but held the substrate at a different temperature for each wafer (25, 100, 200, 300 °C), so the only variable was how large the aluminum crystals grew.

Each chip holds eight quarter-wavelength CPW resonators (center conductor 30 µm, gap 15 µm, near 50 Ω, designed for 5.5–7 GHz with coupling quality factors of (1.5–5) × 10⁵) coupled to a shared feedline, with 4 µm flux-trapping holes on a 6 µm pitch. Aluminum was patterned with AZ 5214E resist and etched in BCl₃/Cl₂ RIE. Then the exposed silicon was treated one of four ways: left unetched; anisotropic CHF₃ RIE with vertical smooth walls; Rtropic (SF₆ at 60 mTorr then CHF₃); or Stropic (SF₆ at 5 mTorr then CHF₃). Samples were measured in a dilution refrigerator at 10 mK with a vector network analyzer and about 116 dB total input attenuation, placing the resonators in the single-photon regime at the lowest drive powers, with no additional magnetic shielding. Surface topography came from a Bruker Dimension Icon AFM in tapping mode (ARROW-NCR cantilever, ~285 kHz), analyzed in Gwyddion with watershed grain segmentation and ISO 21920-2:2021 profile roughness definitions.

Why This Matters

The work converts two vague "interface quality" problems into specific, controllable fabrication knobs, and shows they act on different loss channels — so they can be tuned independently rather than traded off blindly. For the aluminum-on-silicon platform that underpins most high-coherence Josephson junction circuits, that is a practical recipe rather than a phenomenological observation.

• Superconducting qubit processors: higher-Q_i resonators and lower-loss aluminum ground planes and capacitor pads feed directly into readout fidelity and coherence.
• Multiplexed readout and resonator arrays: frequency trimming by local etching allows resonators to be placed on target frequencies after fabrication, useful for dense multiplexed layouts.
• Quantum sensing and microwave hardware: low-loss superconducting resonators are shared components in many cryogenic microwave experiments, not only quantum computing.
• Foundry process development: the grain-size and etch-chemistry levers are standard deposition and RIE steps, so they are compatible with scalable semiconductor fabrication.

Industry relevance: The techniques use conventional e-beam evaporation, photolithography, and RIE — no exotic equipment — making them relatively straightforward to transfer into superconducting circuit foundry flows where yield and frequency targeting are major cost drivers.

Future Directions

• Applying the same aluminum deposition temperatures and Tropic etch to full qubit devices to measure whether coherence times improve proportionally to resonator Q_i, which this paper does not report.
• Resolving the trade-off between larger grains and the substantial surface roughness they introduce (roughly 165 nm peak-to-peak at 300 °C), for example by exploring post-deposition planarization or alternative grain-growth routes.
• Testing whether the grain-boundary and dielectric-trimming strategies generalize to other superconductors and substrates, as the authors expect, and to frequencies beyond the 6.5–8.1 GHz range studied here.
• Understanding why the improvement persists at higher frequencies where prior aluminum-on-silicon work saw larger-grain benefits vanish around 5.9 GHz, and whether magnetic shielding or flux management would add further gains in the unshielded measurement configuration used.

Target Audience

Graduate students and researchers in superconducting quantum computing and quantum device fabrication, process engineers working on cryogenic microwave circuits, and materials scientists interested in how thin-film microstructure and etch chemistry translate into microwave loss. Readers without background in quality-factor measurements or RIE processing will find the fabrication details dense, but the central argument — grains control non-TLS loss, edges control TLS loss — is accessible.

Authors’ abstract

Material losses in superconducting circuits fundamentally limit qubit coherence times and resonator quality factors. Most research efforts focus on mitigating losses at circuit interfaces, including metal--substrate, substrate--air, and metal--air interfaces. However, the correlation between TLS and non-TLS losses with the intrinsic properties of the superconducting metal and the dielectric edge smoothness is not well studied. In this work, we link the aluminum film grain size to non-TLS losses and the dielectric trimming profile and roughness to TLS loss; both loss mechanisms are subsequently mitigated. To reduce metal-related losses, we engineer the aluminum microstructure by heating during deposition, increasing grain size and reducing grain boundary density. Beyond mitigating metal losses, we introduce a two-step etching technique, Tropic etching, to suppress dielectric TLS loss by producing an ultra-smooth silicon surface with minimal defects and redeposition. These results lay out the fabrication pathway for aluminum resonators with lower loss, demonstrating two-orders-of-magnitude improvement in quality factor from $6\times10^{4}$ to $2.3\times10^{6}$. Since aluminum is the basis for most high-coherence Josephson junctions and dielectric edges are inherent to all common device geometries, the improvements in aluminum microstructure and edge profiling, presented here, can enhance the performance of superconducting quantum devices.