Logical gate set tomography

AI summary

Overview

Research area: Quantum error correction (QEC) and quantum characterization, verification, and validation (QCVV), specifically gate set tomography applied to logical qubits in trapped-ion hardware.

Technical level: Advanced. The paper assumes familiarity with quantum channels (CPTP maps), Pauli transfer matrices, stabilizer codes, and maximum likelihood estimation, though its central questions are stated clearly enough for a motivated non-specialist.

Scope (one sentence): The paper introduces "logical GST," a self-consistent tomographic protocol for estimating a complete model of a logical gate set, and applies it to a universal single-qubit logical gate set in the seven-qubit Steane code on Quantinuum's 20-qubit H1-1 trapped-ion processor plus high-shot emulator data.

What This Paper Is About

Quantum error correction reduces noise on logical qubits but does not eliminate it, and the residual logical noise may be coherent or non-Markovian rather than the simple Pauli-stochastic noise usually assumed. The authors ask whether one can experimentally and self-consistently reconstruct what logical gates actually do, rather than just how often they fail. Their goal is to produce a full model of a logical gate set from which fidelity, diamond distance, and tests of Markovianity and coherence can all be derived from one dataset.

Key Contributions

1. A logical GST protocol. The authors adapt standard gate set tomography from physical qubits to encoded qubits. A logical gate set — logical state preparation, logical measurement, and logical gates — is estimated as Pauli transfer matrices plus state/effect vectors via maximum likelihood estimation, with no trusted pre-calibrated reference frames required. The paper states the conditions (syndrome reset, traceability of the syndrome subsystem) under which logical operations can be treated as maps acting on the logical degree of freedom alone.

2. The first full, self-consistent characterization of a universal single-qubit logical gate set. The gate set comprises logical |0⟩_L preparation, logical Z-basis measurement, the transversal Clifford gates H_L (= H^⊗7) and S_L (= (S†)^⊗7), a nontransversal T_L (Z_{π/4}) implemented by magic-state injection with a teleportation gadget, and I_L defined as a QEC cycle — realized in the [[7,1,3]] Steane code on H1-1.

3. Statistical tests for logical non-Markovianity and coherent logical error. Using model-violation statistics (N_σ), a single-parameter wildcard error model, and an AIC-based evidence ratio, the paper tests whether a fixed Markovian logical model suffices, and separately quantifies coherent over-rotation in each logical gate.

4. Error attribution with a detailed device emulator. By selectively disabling physical leakage and coherent memory error in Quantinuum's H1-1E emulator, the authors trace logical error mechanisms back to specific physical sources, and use automated model selection (Sec. VI) to build a reduced logical error model retaining only parameters needed to predict logical circuit behavior.

Main Findings

• Logical performance on H1-1. Entanglement infidelity and diamond-distance error (95%, 2σ intervals) were: H_L 0.7 ± 0.4% and 1.3 ± 1.9%; S_L 0.2 ± 0.4% and 1.3 ± 2.5%; I_L 1.7 ± 9.2% and 3.2 ± 16.8%; T_L 1.2 ± 1.5% and 2.1 ± 3.9%; initialization |0⟩_L 0.0 ± 2.3% (state infidelity); measurement M^Z_L 0.1 ± 1.4% and 0.7 ± 2.1%. At 95% confidence, non-idle logical Cliffords and logical measurement have ε_F ≤ 1.5% and ε_⋄ ≤ 4%; T_L has ε_F ≤ 2.7% and ε_⋄ ≤ 6%; initialization has ε_F ≤ 2.3%.

• Transversal gates behave comparably. H_L and S_L show error metrics that agree within the quoted 95% confidence intervals, as expected for transversal implementations.

• Hardware shows no significant logical non-Markovianity. The CPTP model violation on H1-1 data was N_σ^CPTP < 2, and errors were predominantly logical Pauli-stochastic, with only weak potential signatures of coherent logical error. The paper explicitly notes that the modest dataset (N_shots ≈ 50) limits statistical power: only large non-Markovian or coherence effects would have been detected.

• The emulator reveals what the hardware data could not. With default H1-1E settings (leakage and memory error both enabled) at N_circuits = 931, N_shots = 14100, model violation was N_σ^CPTP ≈ 5. Disabling leakage with memory error retained gave ≈ 2.3; enabling leakage with memory error disabled gave ≈ 2.6; disabling both gave ≈ 1, consistent with no significant logical non-Markovianity. The default emulator data showed strong evidence of coherent logical error.

• Detectable but small effect sizes. Wildcard estimates show the unmodeled error required to reconcile the Markovian model with the data is less than 1% of the per-operation diamond-distance error, so an approximate Markovian gate-set model captures the dominant logical error dynamics even when non-Markovianity is statistically detectable.

• Coherent logical error traces to physical memory error. Selectively disabling physical error sources identified coherent physical-qubit memory errors as the primary cause of the coherent logical error seen in the emulator.

• Non-Markovianity has two origins. Logical non-Markovianity can be inherited from physical leakage and can also emerge from Markovian physical noise. Appendix E reports that with both leakage and memory error off, non-Markovian dynamics were detected at low circuit depth but not at higher ones, suggesting transient emergent logical non-Markovian noise; the authors describe the interplay as an open subject.

• The T_L model is conditional. Because shots failing the flagged |T⟩_L post-selection are discarded (average acceptance rate 95.9% per T_L gate on H1-1, one attempt per preparation), the fitted T_L is an effective trace-preserving operation conditioned on acceptance, not the unconditional operation.

Methodology in Plain English

Reduce the encoded device to a logical description. A stabilizer code splits the data-qubit Hilbert space into logical and syndrome parts (one logical qubit plus six syndrome degrees of freedom for the Steane code). If syndrome extraction and recovery genuinely reset the syndrome subsystem after each gate, it can be traced out, leaving an effective map on the logical qubit alone. If syndrome information persists between gates, the syndrome subsystem acts as a memory and the logical-only picture breaks down — which is exactly the kind of effect the protocol is designed to detect.

Borrow the GST circuit structure. Each circuit is: an effective logical state preparation, a short "germ" sequence repeated p times to amplify errors, and an effective logical measurement. Fiducial sequences of logical gates generate informationally complete preparations and measurements, since QEC typically offers only one native logical preparation and measurement. Circuits with p = 0 characterize the effective null operation, letting state-preparation and measurement errors be modeled self-consistently instead of being blamed on gates. Outcome frequencies are fit with maximum likelihood estimation in the pyGSTi package, and results are reported in a gauge fixed relative to the target gate set.

Compress the experiment to fit the hardware. Each fault-tolerant QEC cycle cost 50 physical two-qubit entangling gates and 12 mid-circuit measurements. The authors used the smallest informationally complete fiducial set, restricted fiducials to transversally implementable gates, applied fiducial pair reduction, capped the germ power at p_max = 32, and limited circuits to at most eight T_L gates. The final design had N_circuits = 158 with N_shots ≈ 50, with circuits averaging 11 QEC cycles and as many as 38 (up to 1900 physical two-qubit gates and 456 mid-circuit measurements from QEC cycles alone). Two circuits were re-executed later to check for drift and were statistically consistent. The dataset is roughly 100× smaller than a typical physical-qubit GST experiment with the same gate set and maximum germ power.

Test the model rather than trusting it. Model violation is quantified as N_σ = (λ − κ)/√(2κ) from the log-likelihood ratio λ, with κ the difference between dataset degrees of freedom and observable model parameters; N_σ ≫ 1 indicates significant violation. A single-parameter wildcard model supplies the effect size that N_σ alone cannot.

Use an emulator as a microscope. H1-1E is a full-stack device model incorporating one- and two-qubit gate errors, measurement bit flips, initialization errors, crosstalk, leakage, and memory errors, with leakage the only non-Markovian physical error and memory error the only modeled coherent physical error. Four high-shot datasets (N_circuits = 931, N_shots = 14100) independently enabled or disabled leakage and memory error, with six Pauli eigenstate fiducials and no fiducial-pair reduction.

Use active error correction. Unlike the earlier implementation in Ref. [72], syndromes are decoded during execution and corrections applied by real-time feedforward rather than Pauli frame tracking — which, the authors note, makes coherent accumulation of logical error more likely to be observed.

Why This Matters

Impact on research. The paper makes logical-error assumptions testable rather than assumed. It provides a protocol that answers "how much logical noise remains?" and "what shape does it take?", giving the QEC community a self-consistent alternative to logical randomized benchmarking (which yields a single average error rate) and to standard state/process tomography (which depends on pre-calibrated reference frames). It also supplies concrete evidence that emergent logical non-Markovianity can arise from strictly Markovian physical noise, and that low-distance codes with hardware-tailored QEC can show non-Pauli-stochastic logical error even where theory predicts twirling to Pauli noise at large code distance.

Real-world applications (implications, not demonstrated deployments):

• Validating and benchmarking fault-tolerant logical operations on early error-corrected processors, beyond memory experiments.
• Calibrating realistic noise models for simulating and compiling logical circuits, so hardware-aware compilation can account for coherent and non-Markovian logical error instead of assuming depolarizing noise.
• Attributing logical error to physical root causes (leakage, memory/transport phase error) to prioritize hardware engineering effort.
• Producing reduced logical error models that retain only the parameters needed to predict logical circuit performance, useful for resource estimation and decoder design.

Industry relevance. The work is a Sandia National Laboratories Quantum Performance Laboratory and Quantinuum collaboration using Quantinuum System Model H1 (H1-1, a 20-qubit trapped-ion processor) and the H1-1E emulator. It gives trapped-ion and other QEC hardware developers a characterization workflow that scales conceptually toward the logical layer, and it demonstrates that emulator-based toggling experiments can diagnose mechanisms that shot-limited hardware data cannot resolve.

Future Directions

• Higher-shot logical GST on hardware. The paper attributes the weak coherence evidence on H1-1 to N_shots ≈ 50; collecting larger experimental datasets is the obvious path to bringing hardware sensitivity in line with the emulator.
• Disentangling leakage and memory-error contributions. The authors state that the interplay between leakage and memory error (and untoggled background errors) in producing logical non-Markovianity "remains a rich subject for further study," and the low-depth-versus-high-depth behavior in Appendix E points to transient emergent non-Markovian noise.
• Extending to multi-qubit and non-Clifford logical gate sets. The demonstrated gate set is single-qubit universal; the protocol could be applied to entangling logical gates and fault-tolerant circuits mixing transversal and nontransversal operations, which the authors flag as potentially exhibiting unexpected effects.
• Validating and improving device models. Since H1-1E may not fully capture some errors or may be overly conservative about others, the authors' conjecture that "leakage off, memory on" best matches H1-1 is an invitation to refine emulator fidelity against tomographic ground truth.

Target Audience

Quantum computing experimentalists and theorists working on error correction and fault tolerance; QCVV methodologists interested in tomography, model validation, and error attribution; trapped-ion and other QEC hardware teams evaluating logical performance; and compiler/simulation researchers who need realistic logical noise models. It is most accessible to readers already comfortable with stabilizer codes and quantum channels, though the introduction frames the core questions in broadly understandable terms.

Authors’ abstract

Quantum error correction (QEC) can strongly suppress noise, but predicting whether a computation succeeds requires understanding not only how much effective noise persists after QEC, but what form that noise takes. To thoroughly characterize this noise, we introduce logical gate set tomography (``logical GST''). Logical GST produces detailed representations of noisy logical operations that can be used to derive higher-level metrics, such as gate fidelity and diamond distance, and to test for non-Markovian and coherent logical errors. We use logical GST to obtain the first full, self-consistent characterization of a universal single-qubit logical gate set, implemented in the seven-qubit Steane code using Quantinuum System Model H1, a 20-qubit trapped-ion quantum processor. In the experimental data from H1, logical GST identified predominantly logical Pauli-stochastic errors, found no evidence of logical non-Markovianity, and detected weak potential signatures of coherent logical error. By contrast, higher-shot datasets generated with Quantinuum's detailed system emulator, identify mechanisms for weak but statistically significant logical non-Markovianity and strong evidence of coherent logical error. Finally, we use logical GST to perform error attribution with the system emulator, revealing how specific physical error sources shape logical error mechanisms.