Layer codes as quantum memories: syndrome extraction, thresholds and idle robustness

AI summary

Overview

• Research area: Quantum error correction — specifically circuit-level fault tolerance of three-dimensional local CSS codes (layer codes) used as active quantum memories.
• Technical level: Advanced. The paper assumes working knowledge of stabilizer codes, syndrome extraction, detector error models, hook errors and belief-propagation decoding.
• Scope (one sentence): The authors build a syndrome-extraction circuit for layer codes, benchmark eighteen such codes against surface codes under identical circuit-level noise and decoding, and report thresholds, idle-time robustness, and hardware demands.

What This Paper Is About

Layer codes are promising 3D-local quantum codes, but prior work characterized only the code — its parameters, distance and passive self-correction — never the noisy circuit that repeatedly measures it. Because layer codes contain weight-5 and weight-6 "junction" stabilizers spanning several planes, a surface code's CNOT schedule and hook-error analysis cannot simply be borrowed. The paper supplies a syndrome-extraction scheduler for these codes and then measures what they actually cost and deliver as actively error-corrected memories under circuit-level noise.

Key Contributions

1. A decoder-free syndrome-extraction scheduler for layer codes. It works in two phases: a geometric rule that constrains hook propagation first (the last CNOT of each stabilizer must act on the data qubit farthest, in lattice distance, from the least-weight of the cleaned logical representatives), followed by a constraint program that assigns ticks and compresses depth to a provably minimal value given detector determinism and the admitted orders. An optional anytime constraint-programming step then minimizes ancilla idle ticks.

2. Circuit generation at scale. Circuits are generated for eighteen layer codes across four input codes (the [[4,2,2]], [[6,4,2]], Steane [[7,1,3]] and Shor [[9,1,3]] input codes), using the YBW26 construction convention, with all comparisons run through an identical pipeline of noise model, detector convention, decoder and scaling fit.

3. Circuit-level threshold measurements. Memory thresholds are extracted by finite-size scaling collapse for four layer code families, alongside rotated and unrotated surface codes run through the same pipeline as references.

4. An idle-robustness benchmark and a hardware-demand analysis. The paper defines a "sustainable idle interval" — the idle time at which one period randomizes the stored logical state with probability 1% — and compares it across codes. It also models the cost of the beyond-2D cross-plane CNOTs the construction requires.

Main Findings

• The scheduler loses no distance to hooks where it can be proven. On the [[4,2,2]] family at d = 4, 5, 6, the authors prove the circuits admit no undetectable logical fault of weight below d, giving d_circ = d in both bases. The minimum residual distance Δ_min also reaches d there, though on the Steane-input code at χ = (3,7,3) it falls one unit short of d_X.

• Lower logical error rate than a general-purpose CSS scheduler at roughly half the CNOT depth. Against the LRC scheduler, the authors' round has CNOT depth 5 at d = 4 and 6 at d = 6 and d = 8, versus 11 at every distance for LRC. Under depth-aware per-tick idle noise, LRC's logical error rate is 6–13 times higher at d = 4, 18–32 times at d = 6, and 25–75 times at d = 8 (X memory). Under depth-agnostic per-round noise the gap is up to 6.5× at d = 6 and 11× at d = 8 — showing most of the advantage comes from the shallower round.

• Primary threshold result, [[4,2,2]] family at χ = (d,d,d), d = 4–8: p_th = 4.99(6) × 10⁻³ in X memory and 5.06(7) × 10⁻³ in Z memory, with ν = 0.86(8) and 0.87(9).

• Surface code references under the identical pipeline: rotated surface code gives 7.71(9) × 10⁻³ (X) and 7.73(14) × 10⁻³ (Z); unrotated surface code gives 8.02(6) × 10⁻³ (X) and 8.29(6) × 10⁻³ (Z). Averaged over bases, the [[4,2,2]] family sits a factor of 1.54 below the rotated and 1.62 below the unrotated surface code.

• Other layer code families converge near the same value. The [[6,4,2]] family at χ = (d,6,d) gives 5.40(4) × 10⁻³ (X) and 5.51(6) × 10⁻³ (Z). The two families agree to within 9%, at 5.0–5.5 × 10⁻³. The Steane family gives 4.19(30) × 10⁻³ (X) and 4.10(35) × 10⁻³ (Z), with larger uncertainties; excluding χ = (4,4,4) tightens the fit to 4.30(18) × 10⁻³ and 4.23(21) × 10⁻³, while excluding χ = (4,7,4) moves it to 3.92(25) × 10⁻³ and 3.80(28) × 10⁻³.

• The Shor-input family is X/Z asymmetric. In X memory (d_Z = 8, 11, 14) it collapses to 3.13(14) × 10⁻³, while in Z memory (d_X = 4, 5, 6) it gives 5.08(29) × 10⁻³ — a compromise fit across a non-self-similar series whose pairwise crossings straddle 3.7 × 10⁻³ to 6.4 × 10⁻³. The asymmetry traces to the input code's X-checks of weight 6 and Z-checks of weight 2.

• The threshold gap is mostly a depth effect, not a hook-quality effect. Under a depth-agnostic per-round idle model, the [[4,2,2]] family reaches 7.01(8)/7.02(9) × 10⁻³, the unrotated surface code 6.98(12)/7.18(10) × 10⁻³ and the rotated 6.89(15)/6.81(21) × 10⁻³ — all within a few percent. The per-tick gap therefore comes mainly from the layer code's deeper syndrome-extraction round.

• Noise-layer accounting. Apparent thresholds for the [[4,2,2]] family are approximately 0.15 (code capacity), 4.0 × 10⁻² (phenomenological), 7.3 × 10⁻³ (per-round circuit-level) and 5.3 × 10⁻³ (per-tick circuit-level). Gate and hook errors cost a factor of roughly 5.5 relative to the phenomenological model, measurement errors roughly 3.7 relative to code capacity, and depth-dependent idle exposure a further roughly 1.4. At p ≈ 4 × 10⁻³ and d = 6, the depth-aware model's LER is roughly 6–8 times the depth-agnostic one.

• Layer codes win on idle robustness. At the same distance the layer code sustains an interval between syndrome extraction rounds 1.7–3.0 times longer than the rotated surface code.

• The price of that robustness is 1.7–5.0 times more two-qubit gates, measurements and noisy locations per logical qubit per unit time, and approximately five times more physical qubits per logical qubit.

• Cross-plane gate speed matters more than its fidelity. Making the required beyond-2D cross-plane CNOTs ten times noisier costs about a factor of two in logical error rate, whereas making them twice as slow costs a five- to seventeenfold penalty.

• Ancilla idle can be almost entirely eliminated. The optional idle-optimization step removes essentially all (100% on 32 of the 36 circuits built, above 93% on the rest) of the propagating ancilla idle ticks; on the [[4,2,2]] family a further minute of optimization removes 94%, 100% and 91% of all live ancilla idle at d = 4, 6, 8.

• Construction cost. For the [[4,2,2]] family at d = 4, 6, 8 (148, 364 and 676 data qubits), building a valid circuit at proven-optimal depth takes 4.0 s, 122 s and 179 s, against 7.5 s, 33 s and 149 s for LRC's full construction; the scheduling step alone takes 1.0 s, 4.9 s and 24 s, with the remainder spent on the minimum-weight ILP supplying logical representatives.

• Robustness checks on the comparison. Refitting both surface code families under BP+OSD moves thresholds by less than 0.6% on the unrotated code and 1–2% upward on the rotated one; swapping the unrotated patches' balanced schedule for a single fixed one leaves the basis-averaged threshold unchanged to 0.2% while swinging the X/Z split by roughly 8 percentage points. BP+LSD is measured to be slightly pessimistic (median LER ratio 1.17 at d = 4 rising to 1.36 at d = 8), so the reported layer code thresholds are conservative.

Methodology in Plain English

• Fix the conventions first. The authors pin down one set of choices — how detectors are placed (mid-circuit detectors only on stabilizers matching the memory basis), how logical observables are represented, how error rates are normalized — and hold them fixed across every code so comparisons are apples to apples.

• Design the measuring circuit instead of borrowing one. Because layer codes have junction stabilizers spanning several planes, the authors write their own scheduler. Phase one uses a geometric heuristic to decide the order of CNOT gates within each stabilizer so that a fault on the ancilla cannot spread into a damaging correlated data error. Phase two treats circuit depth as an optimization problem, packing gates into as few time steps as possible while respecting the chosen orders, then tightening each ancilla's reset and measurement so it is not sitting idle producing noise.

• Simulate under realistic noise. Every operation — idling, one- and two-qubit gates, initialization, measurement — can fail. The default model charges noise per time tick, so a deeper circuit is penalized, which is the physically honest choice.

• Decode globally and identically. All circuits are decoded with belief propagation plus a localised-statistics post-processor (BP+LSD) acting directly on the raw detector error model, keeping hyperedges intact rather than breaking them into graphlike pieces. BP+OSD is used only as an accuracy reference where circuits are small enough.

• Extract thresholds by collapsing curves. Logical error rate is sampled across each family's crossing region and all distances in a family are fit jointly as a function of (p − p_th)·d^(1/ν), yielding both the threshold and the exponent.

• Test idle robustness separately. A logical state is prepared, then a repeating period applies a few syndrome-extraction rounds followed by an idle hold, read out at the end. The sustainable idle interval is where one period randomizes the logical state with probability 1%.

• Model the hardware demand. The beyond-2D cross-plane CNOTs the construction needs are given extra noise and extra slowness separately, to see which penalty dominates.

Why This Matters

• It moves layer codes from "a good code" to "a runnable memory." Claims about a code's parameters say nothing about whether a noisy circuit measuring it preserves its distance. This paper supplies the missing circuit and the first circuit-level threshold numbers for the family.

• It separates two failure mechanisms that are often conflated. By rerunning with depth-agnostic idle noise, the authors demonstrate that the threshold gap to surface codes is dominated by circuit depth rather than by the hook structure of the junctions — a finding that redirects effort toward scheduling and hardware speed rather than toward code redesign.

• It identifies a resource trade that architectures can plan around. Trading roughly five times the physical qubits and 1.7–5.0 times the operations per unit time for a 1.7–3.0 times longer tolerable idle interval is a concrete design decision for systems where syndrome extraction is expensive or slow.

• Real-world applications:

  • Fault-tolerant quantum processor design, where choosing between planar and multi-layer code architectures determines qubit counts and control wiring.
  • Cryogenic control and interconnect engineering, since the results show cross-plane gate speed dominates over gate fidelity.
  • Architectures with slow or costly measurement, such as systems with limited readout bandwidth or long reset/measurement times, where long sustainable idle intervals matter most.
  • Compiler and control-stack scheduling, because the idle-robustness metric maps directly onto how often a machine must interrupt other operations to refresh a memory.

• Industry relevance: The result that gate speed outweighs gate fidelity for cross-plane couplers is directly actionable for hardware groups deciding whether to invest in faster couplers or cleaner ones, and the five-times-qubit overhead sets a concrete bar for when a 3D-local code becomes preferable to a surface code.

Future Directions

• Close the remaining distance gap on non-[[4,2,2]] inputs. On the Steane-input code at χ = (3,7,3), Δ_min falls one unit short of d_X; a scheduler or proof technique that recovers full circuit distance there is an open problem.

• Beat the depth penalty. Since the threshold gap to surface codes nearly vanishes under depth-agnostic noise, any further reduction in the layer code's syndrome-extraction round depth would buy threshold directly — the paper notes the residual idle term bounds what further depth work could buy.

• Handle X/Z-asymmetric inputs. The Shor-input series shows the input code's asymmetry propagates into the threshold itself (3.13(14) × 10⁻³ in X memory versus 5.08(29) × 10⁻³ in Z memory); how to schedule or tune χ for such families is unresolved.

• Replace plane-decomposed decoding. The authors note that per-plane matching decoders previously proposed for layer codes rely on decompositions and lose accuracy under circuit-level noise, with Section VI.1 quantifying this — leaving room for better global decoders at scale, since BP+OSD was affordable only as a cross-check here.

Target Audience

Researchers and graduate students in quantum error correction and fault-tolerant architecture design; hardware teams evaluating 3D-local or multi-layer code architectures against the planar surface code; and engineers working on cryogenic control, cross-plane couplers and syndrome-extraction scheduling. Readers need a working grasp of stabilizer codes, hook errors and detector error models to follow the technical arguments, though the headline trade-offs (thresholds, qubit overhead, idle intervals, gate speed versus fidelity) are accessible to a broader quantum-computing audience.

Note: the supplied paper text is truncated partway through Section IV.2, so the full details of Sections V and VI — including the complete hardware model and the collected list of unsuccessful routes — are not reported here.

Authors’ abstract

Layer codes are three-dimensional local CSS codes of check weight at most six, obtained by quasi-concatenating a CSS input code with unrotated surface code patches. What is established about them describes the code, not the circuit that measures it. In this work, we evaluate them as active memories under circuit-level noise. Doing so first requires a syndrome extraction circuit, and the junction stabilizers that couple the patches rule out borrowing a surface code patch's CNOT schedule. We present a decoder-free scheduler that constrains hook propagation first and compresses depth afterwards, generate circuits for eighteen layer codes across four input codes, and compare them with surface codes of the same distance, simulated and decoded in the same way. The circuits lose no distance to hook errors on [[4,2,2]]-input codes wherever a circuit-distance proof is affordable, and reach a lower logical error rate than those of a general-purpose scheduler for CSS codes at roughly half its CNOT depth per round. Our primary family built from a [[4,2,2]] input code reaches a circuit-level threshold of $5.06(7)\times10^{-3}$. The layer code outperforms the surface code in terms of idle robustness: at the same distance it tolerates an interval between syndrome extraction rounds 1.7-3.0 times longer than the rotated surface code. This comes at the cost of 1.7-5.0 times more operations per unit time and approximately five times more physical qubits, both per logical qubit. Finally, we model the cost of the beyond-2D cross-plane CNOTs that the construction demands, and find that their speed matters far more than their fidelity.