High-rate qLDPC processors

AI summary

Overview

Research area: Quantum error correction and fault-tolerant quantum computing, specifically quantum low-density parity-check (qLDPC) codes and the logical-operation layer (surgery, magic-state injection, decoding) needed to turn a code into a processor.

Technical level: Advanced. The paper uses group algebras, lifted-product codes, and circuit-level decoding benchmarks; the summary below keeps the concepts accessible but the underlying material assumes familiarity with stabilizer codes.

Scope (one sentence): The paper introduces "mitten codes," a family of non-abelian lifted-product qLDPC codes with 20% encoding rate and check weight 9, and demonstrates through large-scale circuit-level simulation that they support universal, highly parallel fault-tolerant logic with fast decoding and plausible mappings to neutral-atom and superconducting hardware.

What This Paper Is About

High-rate qLDPC codes can store quantum information with far fewer physical qubits than the surface code, but a memory is not a processor: a useful device must also support flexible logical operations, run many of them in parallel, map onto real hardware, and be decoded quickly and accurately. The authors argue that these four requirements (high encoding rate, high throughput, hardware compatibility, fast and accurate decoding) are usually optimized in isolation, and they set out to build a code family that satisfies all four at once.

Key Contributions

1. Mitten codes. A family of lifted-product codes LP(A,B) built from 1×2 base matrices over the group algebra F₂[G] of a non-abelian group G, with guaranteed 20% encoding rate and check weight 9. Non-abelian structure evades the distance-6 upper bound that the authors show afflicts all abelian constructions with the same base-matrix shape, allowing distances of 18 and beyond at a few hundred data qubits. Eight instances are reported, from ⟦150,30,10⟧ to ⟦975,195,≤24⟧.

2. A symmetry-derived logical toolkit. A canonical logical basis {X̄_g, Z̄_g} indexed by group elements, where every logical operator is a group-action image of the identity-element representative. This yields five reusable gadgets for universal Clifford processing (built from just two seed gadgets for X̄ and Z̄, plus bridging), a single fixed full extractor as an alternative, high-rate surgery measuring up to k/2 disjoint weight-two Pauli products in parallel, and parallel magic-state injection into all logical qubits simultaneously.

3. A telescoping decoder and billion-shot benchmarking. A staged decoder combining many rounds of belief propagation (BP) and Relay-BP with a final exact integer-programming stage, with custom CUDA kernels on GPU and C kernels on CPU, benchmarked on the ⟦144,12,12⟧ gross code against Tesseract and Cascade.

4. An end-to-end processor discovery pipeline built on sQetch. A three-level pipeline (algebraic search, fault-tolerance validation, gadget and hardware construction) that turns a target specification into a complete processor design, using a new GPU-based distance estimator, sQetch, reported as up to 800,000 times faster than current state-of-the-art methods. The toolkit is open-sourced.

Main Findings

• Threshold: Under circuit-level depolarizing noise with no idling noise, the mitten code family shows numerics consistent with an effective finite-size threshold of p_c ≈ 0.7%.
• Memory at 0.1% physical error rate: The ⟦300,60,14⟧ code reaches a block logical error rate of 9.5^{+21.8}_{-7.9} × 10⁻¹² per syndrome extraction round — one logical error observed in over 100 billion rounds.
• Memory at 0.4% physical error rate: The ⟦975,195,≤24⟧ code attains 4.2^{+5.5}_{-2.7} × 10⁻⁸ per round, matching a ⟦112320,195,24⟧ stack of rotated surface codes decoded with correlated matching while using two orders of magnitude fewer physical qubits.
• Surgery at scale: Directly decoding 15 billion surgery experiments on the ⟦540,108,18⟧ code at 0.1% physical error rate produced only two logical failures, a logical error rate of 1.33^{+1.76}_{-0.86} × 10⁻¹⁰ per quop, consistent with a ten-billion-quop processor.
• Giga-quop operation: On the ⟦300,60,14⟧ code, single X̄ measurements, joint X̄X̄ measurements, and a high-rate gadget measuring ten X̄X̄ products in parallel produced two logical errors across one billion X̄X̄ operations and none in the remaining experiments.
• Gadget overhead is small: The five reusable Clifford gadgets are distance-preserving and increase the maximum check weight by at most three; the full extractor keeps every merged check weight at most 14.
• Error structure: Every logical error observed in the X basis is a timelike error in the measured operator itself, so the authors suggest these rates can likely be suppressed further by increasing the number of syndrome extraction rounds.
• Decoder quality: On gross-code memory experiments, the telescoping decoder matches or improves on state-of-the-art decoders including Tesseract and Cascade, with nearly twice the throughput of the neural decoder closest to it in accuracy.
• Latency: Each window of O(d) syndrome extraction rounds decodes with sub-millisecond average latency in both memory and surgery experiments, sufficient for real-time decoding on neutral-atom hardware.
• Hardware mapping: On superconducting layouts the codes have a hardware complexity metric C_hw (surface code normalized to 1) ranging from 2.02 to 3.40 across the eight instances, comparable to the ⟦144,12,12⟧ gross code at 2.12 and the ⟦288,12,18⟧ two-gross code at 2.24 for comparable block size, while achieving much higher encoding rate.

Methodology in Plain English

The authors build codes from a "lifted product" of two small classical matrices whose entries are elements of a group. Concretely, five blocks of data qubits are each of size |G|, with two blocks of X-check ancillas and two blocks of Z-check ancillas; the group's left- and right-multiplication rules determine exactly which qubits each check touches. Choosing a non-abelian group matters: with an abelian group, a low-weight codeword of the base matrix directly produces a low-weight logical operator, capping distance at the check weight; non-abelian structure removes that shortcut.

Because the logical operators form a single orbit under the group action, the authors only need to design gadgets for one X̄ and one Z̄, then "rewire" them by group multiplication to address any logical qubit. They combine these seeds into weight-two and Ȳ gadgets, and separately design parallel surgery and a magic-state injection scheme that teleports distance-d_rep surface-code magic states into all logical qubits at once through an intermediate code that interfaces the patches with the mitten code.

For performance, they simulate circuits in Stim under uniform depolarizing noise, generate detection events, and pass shots through the telescoping decoder: cheap GPU stages handle most shots, harder shots are escalated through finer-grained decoding (using the GARI transform of the correlated detector error model) and finally to an exact integer-programming solver. To find good codes in the first place, they run a pipeline that prunes the space with theoretical distance bounds, brute-force searches survivors with sQetch, then verifies syndrome-extraction schedules at the circuit level and constructs gadgets and hardware layouts.

Why This Matters

Impact on research: The paper reframes qLDPC evaluation around processor-level metrics — processing capacity (1/p_L), throughput in quops per logical cycle, and cycle time — rather than code parameters alone. It shows that a small-block, 20%-rate non-abelian code can host a complete universal instruction set with a handful of reusable gadgets, and it supplies a decoder and design pipeline that make billion-shot, no-extrapolation benchmarking feasible.

Potential real-world applications (as motivating contexts, not demonstrated deployments):

• Fault-tolerant quantum simulation of chemistry and materials problems, where logical error rates orders of magnitude below physical error rates are required.
• Cryptanalysis and other algorithms needing long chains of reliable logical operations (the ten-billion-quop regime simulated here).
• Modular, tiled quantum processors assembled from many identical small code blocks rather than one monolithic device.
• Neutral-atom and superconducting hardware programs that need codes matching their native connectivity and atom-shuttling capabilities.

Industry relevance: The explicit neutral-atom syndrome-extraction cycle-time estimates, the superconducting hardware-complexity analysis, the real-time decoding latency target, and the open-sourced design toolkit are aimed at groups building actual machines, not only at theory.

Future Directions

• Hardware demonstration. The paper provides layouts and cycle-time estimates for neutral-atom and superconducting platforms, but no experimental realization is reported; validating the predicted logical error rates on real devices is the obvious next step.
• Exact distances for the largest codes. The ⟦630,126,≤20⟧, ⟦780,156,≤22⟧, and ⟦975,195,≤24⟧ distances are upper bounds estimated from over 50 million sQetch iterations and over 50 thousand BP+OSD iterations, not exact values.
• Pushing processing capacity further. Since observed X-basis logical errors are timelike, increasing the number of syndrome extraction rounds is proposed as a route to lower logical error rates and higher quop counts.
• Real-time decoder deployment. The staged decoder is argued to extrapolate to real-time operation based on mapping stages onto existing FPGA implementations, but the end-to-end real-time system is estimated rather than built.

Target Audience

Quantum error-correction researchers and graduate students; fault-tolerant architecture and compiler engineers; experimentalists working on neutral-atom arrays or superconducting qubits who need concrete code-and-gadget proposals with overhead numbers; and technical leaders assessing the resource costs of high-rate qLDPC approaches relative to the surface code.

Authors’ abstract

Despite significant progress on quantum low-density parity-check (qLDPC) codes, building qLDPC processors that are high-rate, high-throughput, hardware-friendly, and fast-to-decode remains a challenge. We introduce mitten codes, a family of qLDPC processor codes of encoding rate $20\%$ and check weight $9$, based on non-abelian groups. Their non-abelian structure evades distance bounds constraining abelian counterparts, allowing mitten codes to reach distance $18$ and beyond with just a few hundred data qubits. The logical operators of a mitten code are related by the group action, yielding a modular, low-overhead logical toolkit: full Clifford operations follow from bridging two reusable seed surgery gadgets or from a single fixed extractor. Furthermore, qLDPC processors based on mitten codes support high-rate surgery that executes many logical measurements in parallel, and parallel magic-state injection into all logical qubits at once. Under circuit-level noise, with our fast decoder, the $[\![300,60,14]\!]$ mitten code achieves, without extrapolation, a block logical error rate of ${\sim}10^{-11}$ per round at $0.1\%$ physical error rate (PER), while the $[\![ 975,195,\leq 24 ]\!]$ code reaches ${\sim}10^{-8}$ at $0.4\%$ PER. Decoding $15$ billion surgery experiments on the $[\![540,108,18]\!]$ code at $0.1\%$ PER, we observe only two logical failures, demonstrating a qLDPC processor capable of running ${\sim}10^{10}$ logical operations. Our decoder is compatible with sub-millisecond average latency per logical cycle, sufficient for real-time decoding on neutral atom hardware. Discovered by an end-to-end design pipeline built on sQetch, a distance estimator orders of magnitude faster than existing tools, and mapping efficiently onto near-term neutral atom and superconducting hardware, mitten codes open a practical path toward fault-tolerant quantum computation.