Ground-state energy estimation compiled on cat qubits: 7 164 qubits for FeMoco-54 in 23.5 hours

AI summary

Overview

Research area: Quantum computing — fault-tolerant resource estimation for quantum chemistry, specifically ground-state energy estimation compiled onto bosonic cat-qubit architectures.

Technical level: Advanced. The paper assumes familiarity with block encodings, lattice surgery, magic state distillation, and biased-noise error correction.

Scope (one sentence): A detailed, closed-form compilation and end-to-end resource estimate of a state-of-the-art sum-of-squares block encoding for the FeMoco-54 and FeMoco-76 electronic-structure Hamiltonians, targeting both a repetition-cat and a hybrid LDPC-cat architecture.

What This Paper Is About

Estimating the ground-state energy of a molecule on a fault-tolerant quantum computer requires turning an abstract algorithm into a concrete physical layout — every lookup table, swap network, rotation, and error-correction step has to be scheduled and costed. Cat qubits make this unusual: because bit flips are exponentially suppressed and only phase flips need correcting, the hardware is cheap in qubits but awkward in which logical operations it supports, so standard surface-code compilations do not carry over. The authors rebuild the compilation from scratch for two cat-qubit architectures, then report full physical qubit counts and runtimes for the FeMoco benchmarks. They treat FeMoco explicitly as a benchmark rather than a demonstration of quantum advantage, since recent classical work has estimated FeMoco-76 to about chemical accuracy by extrapolation at an idealized cost of under a minute on the Frontier supercomputer, and FeMoco-54's ground-state energy was already shown to be classically accessible.

Key Contributions

1. Closed-form compilations of the dominant subroutines on cat qubits — the skew-tree QROM, a Swap network (described as the first compilation of swap networks on cat-qubit architectures, with some X^(1/2) corrections from state injection merged into one per address qubit), and a Phaseup with a strategy that minimizes the number of phase gates and hence Clifford resource states consumed.

2. An X-basis ("color-changed") representation of algorithmic qubits that exploits the asymmetric cost of X versus Z access in cat-qubit codes: in this convention a Toffoli becomes a C_X C_X Z gate and a multi-target Cnot becomes a parity-controlled Not, letting address and system registers be stored densely in the repetition-cat architecture and accessed more easily in the LDPC-cat architecture.

3. New distillation protocols and factories — a protocol for |i⟩-state distillation in repetition codes (based on earlier work), plus two-level Toffoli-like |C_X C_X X⟩ magic state distillation with three pipelined factory layouts reaching output error rates of about 10^-11 at p_Z = 10^-3 and 2×10^-13 at p_Z = 5×10^-4.

4. Global layouts and end-to-end resource counts for FeMoco-54 and FeMoco-76 on both architectures, using the adder compilation from the companion work of Pappalardo et al., plus a more precise logical error model of the LDPC-cat codes obtained from new circuit-level simulations.

Main Findings

• Headline FeMoco-54 result: under a 1 µs cycle time, 10 µs reaction time, 1 mHa phase-estimation precision, and circuit-level phase-flip noise p_Z = 5×10^-4 with negligible bit-flip error, FeMoco-54 requires 7,164 cat qubits with an expected runtime of under one day (0.98 d in Table 1) for a single phase estimation run on the LDPC-cat architecture when system qubits are reused as dirty ancillae. Without dirty ancillae the same 7,164-qubit footprint takes 1.10 d and 2.91×10^9 Toffolis.

• The 23.5-hour figure corresponds to the roughly 0.98-day runtime for that 7,164-qubit, 2.01×10^9-Toffoli LDPC-cat configuration.

• Full Table 1 comparison (p_Z = 5×10^-4, d_LDPC = 16, d_rep = 15, λ = 2):

  • Repetition-cat, no dirty ancillae: FeMoco-54 — 11,192 qubits, 2.89×10^9 Toffolis, 0.95 d; FeMoco-76 — 12,568 qubits, 1.36×10^10 Toffolis, 4.49 d.
  • Repetition-cat, with dirty ancillae: FeMoco-54 — 13,028 qubits, 1.99×10^9 Toffolis, 0.68 d; FeMoco-76 — 15,152 qubits, 6.70×10^9 Toffolis, 2.20 d.
  • LDPC-cat, no dirty ancillae: FeMoco-54 — 7,164 qubits, 2.91×10^9 Toffolis, 1.10 d; FeMoco-76 — 7,818 qubits, 1.38×10^10 Toffolis, 5.09 d.
  • LDPC-cat, with dirty ancillae: FeMoco-54 — 7,164 qubits, 2.01×10^9 Toffolis, 0.98 d; FeMoco-76 — 7,818 qubits, 6.94×10^9 Toffolis, 3.31 d.

• Architecture comparison: at p_Z = 5×10^-4 and comparable runtime, the LDPC-cat architecture gives a space footprint reduction of 36% to 38% relative to repetition-cat for both FeMoco-54 and FeMoco-76.

• Smaller repetition-cat footprint via a larger compute zone: for FeMoco-54, loading λ = 3 rotation angles at a time reduces runtime enough that the code distance can drop to d = 13 (versus d = 15 at λ = 2), yielding the smallest repetition-cat footprint of 11,176 physical qubits at 14.8 hours.

• Smallest spacetime volumes: 0.088 megaqubit-hours for FeMoco-54 (LDPC-cat, λ = 9) and 0.314 megaqubit-hours for FeMoco-76 (LDPC-cat, λ = 19).

• Relaxing the bit-flip assumption: when the bit-flip requirement is relaxed to p_X = 10^-11 with an additional layer of elevator codes, the estimate rises to about 13,000 cat qubits.

• Where the cost sits: in the repetition-cat architecture, Z access requires an access corridor of d data qubits alongside the code and is therefore paid in space; in the hybrid LDPC-cat architecture a shared routing layer provides Z access, so congestion is paid in time instead.

Methodology in Plain English

The authors do not invent a new quantum algorithm for chemistry. They take an existing state-of-the-art approach — a double-factorized tensor hypercontraction (DFTHC) representation that writes the Hamiltonian as a sum of squares, block-encoded and combined with spectral amplification — and reuse the same Hamiltonians, DFTHC parameters, and precisions as prior work, then focus entirely on the engineering layer that sits between algorithm and silicon.

Two facts about cat qubits drive every design decision. First, cat qubits are biased: bit flips are exponentially suppressed while phase flips grow only linearly, so the correction code only has to handle phase flips, and either a classical repetition code or a classical 2D-implementable LDPC code suffices. That makes per-logical-qubit overhead grow linearly with distance for repetition codes, and better still for LDPC codes. Second, this efficiency comes with a restricted gate set: since the codes use only X-type stabilizers, lattice surgery is limited to X-type Pauli measurements, Z-type operations rely on the bias-preserving Cnot, and the X logical operator can be touched via a single physical data qubit while Z access requires reaching several qubits.

The central trick is to flip the usual convention and represent algorithmic qubits in the X basis. Address and system registers then need mostly X access, which is cheap, so they can be packed densely and reached easily. On top of this convention the authors compile each primitive — QROM via a skew tree, swap networks, phase-gradient (Phaseup) circuits — write down closed-form qubit and gate counts, and design injection gadgets per subroutine so that Clifford corrections from magic state injection are as cheap as possible. They introduce distillation factories for the required resource states, including |i⟩ states and the two-level Toffoli-like |C_X C_X X⟩ state.

Finally, they assemble complete layouts: Toffolis run serially from a single two-level factory, the algorithmic region's footprint is set by its largest subroutine, remaining choices are made to minimize runtime, and the code distance is chosen by minimizing expected runtime. A "compute zone" parameter λ (how many rotation angles are loaded at once) is swept to trace a space–time trade-off curve, with λ = 2 as the reference configuration.

Why This Matters

The paper quantifies what a biased-noise, cat-qubit machine would actually cost for a canonical chemistry benchmark, and does so at the level of physical qubits, Toffoli counts, and hours rather than abstract logical qubit counts. Its distinctive claim is that architecture details — corridor space versus routing-layer time, X versus Z access asymmetry — change the optimal compilation, not just the constant factors, so resource estimates must be redone per architecture rather than transplanted from surface-code studies.

Real-world applications of the underlying capability:

• Catalysis and nitrogen fixation: FeMoco is the iron-molybdenum cofactor of nitrogenase, the enzyme that fixes atmospheric nitrogen; accurate ground-state energies are the target of electronic-structure simulation for catalysis.
• Transition-metal chemistry: the benchmark is representative of strongly correlated systems with transition-metal centers, a notoriously hard class for classical methods.
• Materials and energy research: the same block-encoding machinery applies broadly to strongly correlated electronic-structure Hamiltonians.
• Benchmarking hardware roadmaps: the space–time trade-off curves give hardware designers concrete targets (qubit counts, cycle times, error rates) for a useful application.

Industry relevance: the work comes from Alice & Bob and is explicitly aimed at superconducting cat-qubit hardware, connecting device-level noise parameters (p_Z, p_X, cycle and reaction times) to application-level runtime — precisely the translation needed for architecture and roadmap decisions in a quantum hardware company.

Future Directions

• Closing the bit-flip gap: the jump from a negligible-bit-flip assumption to p_X = 10^-11 with an added elevator-code layer costs roughly a factor of two in qubits (7,164 to about 13,000), so cheaper bit-flip protection is an open engineering question.

• Tighter magic state factories and injection gadgets: the three pipelined |C_X C_X X⟩ factory layouts and the per-subroutine injection gadgets are the main lever on Clifford-correction overhead; further improvements in output error rate or throughput would directly reduce runtime.

• Refining logical error models: the authors supply a more precise LDPC-cat logical error model from new circuit-level simulations, but the estimates still rest on a phase-flip-only circuit-level noise model, leaving room for more complete noise treatments.

• Better space–time operating points: the compute-zone sweep shows that the smallest footprint, fastest runtime, and smallest spacetime volume occur at different λ values (λ = 2 reference, λ = 9 and λ = 19 for spacetime minima), suggesting room to co-optimize layouts jointly with the adder compilation from the companion work.

Target Audience

Quantum-computing researchers and engineers working on fault-tolerant resource estimation, biased-noise and bosonic qubit architectures, and compilation for lattice surgery. It is most useful to readers already comfortable with block encodings, magic state distillation, and error-correction code parameters; the chemistry content is taken as fixed input rather than developed. Hardware architects and roadmap planners at quantum computing companies will find the space–time trade-off curves and the explicit noise assumptions directly actionable.

Authors’ abstract

We provide a detailed resource estimate of the state-of-the-art sum-of-squares block encoding algorithm for electronic structure Hamiltonians of Low et al. on superconducting cat qubits. To achieve this, we present compilations with closed-form costs of the dominant subroutines such as skew-tree Qrom, a Swap network and a Phaseup for both a repetition-cat and an LDPC-cat architecture. Our compilation represents algorithmic qubits in the $X$ basis, taking advantage of the asymmetric cost of $X$ and $Z$ access that the concatenation of cat qubits with phase-flip classical code brings. Additionally, we provide a protocol for $\vert i \rangle$-state distillation and a two-level Toffoli-like $\vert \text{C}_X\text{C}_X X \rangle$ magic state distillation protocol, including three factory layouts. To minimize the cost of Clifford corrections induced by magic state injections we tailor injection gadgets to each subroutine. Combining our compilation work with the adder compilation from the companion work Pappalardo et al., we provide global layouts for the block encoding in both architectures which we use to obtain resource estimates for ground-state energy estimation for the benchmarks of FeMoco-54 and FeMoco-76. Assuming a cycle time of 1$μ$s, a reaction time of 10$\mathrmμ$s, a phase estimation precision of 1 mHa and circuit-level phase-flip noise with probability $p_Z = 5 \times 10^{-4}$ with negligible bit-flip error, FeMoco-54 requires fewer than $7\,500$ cat qubits with an expected runtime of under one day for a single phase estimation run using an LDPC-cat architecture. Relaxing the bit-flip requirement to $p_X = 10^{-11}$ with an additional layer of elevator codes raises this to an estimated $13\,000$ cat qubits.