FIREQ: FPGA Instrumentation for Readout and Qubit control

AI summary

Overview

Research area: Quantum computing hardware — classical control and readout electronics for superconducting qubits, specifically FPGA/Radio Frequency System-on-Chip (RFSoC) instrumentation.

Technical level: Advanced. The paper assumes familiarity with superconducting qubit physics (dispersive readout, Bloch sphere, Rabi/Ramsey experiments), digital signal processing (DDS, IQ modulation, decimation), and FPGA design flows (AXI peripherals, BRAM/URAM/DSP resources).

Scope: The paper presents FIREQ, an open-source RFSoC-based firmware and software framework for controlling and reading out superconducting qubits, and characterizes it in terms of RF performance, FPGA resource usage, and end-to-end qubit measurements.

What This Paper Is About

As superconducting quantum processors grow to more qubits, the room-temperature electronics needed to drive and measure them become a major bottleneck in cost, cabling, synchronization, and data throughput. FIREQ addresses this by integrating pulse generation, acquisition, signal processing, and timing into a single programmable RFSoC platform, with a modular firmware built from standard AXI peripherals and a Python-based client–server software stack. The goal is a resource-efficient, extensible control platform that can also serve as a testbed for evaluating alternative control and readout IP architectures.

Key Contributions

1. The FIREQ framework itself: a flexible, expandable qubit control and readout framework built from AXI-compliant peripherals, designed to reduce hardware resource utilization and simplify system reconfiguration. It is released open source (client software, server software, executable RFSoC bitstream, and documentation at https://fireq-docs.polito.it, archived via versioned Zenodo records).

2. An envelope interpolation technique: an on-the-fly linear interpolation method (DDS with first-order Taylor correction) that reconstructs pulse envelopes from a reduced set of stored reference samples, cutting waveform-memory requirements and enabling envelope reuse across different rotations.

3. Memory-efficient acquisition buffering: decimated and accumulated acquisition buffers are mapped to UltraRAM (URAM), reserving higher-bandwidth BRAM for datapaths with stricter throughput requirements.

4. An integrated software stack: a modular PYNQ-based stack with standardized hierarchical configuration and dependency resolution, supporting hardware reconfiguration with minimal changes.

5. Comprehensive RF characterization and qubit-level validation: phase noise, noise spectral density, inter-channel timing skew, FPGA resource comparison against other open-source frameworks, and validation through resonator spectroscopy, Rabi, Ramsey, and relaxation measurements.

Main Findings

• RF generation range and resolution: On an AMD Zynq UltraScale+ RFSoC ZCU216, FIREQ generates RF pulses up to 9.3 GHz, with a pulse-duration resolution of 107 ps and an event-timing resolution of 1.7 ns.

• Full-rate conversion: RF DACs and ADCs operate close to their maximum sampling frequency (9.34 GSps and 2.33 GSps respectively), with no interpolation or decimation used to reduce the working throughput of the signal generation and acquisition IPs.

• Low total FPGA footprint: FIREQ uses 32 774 total LUTs, 27 796 logic LUTs, 552 LUTRAMs, 4 426 SRLs, 57 992 FFs, 132.5 BRAM, 2 URAM, and 380 DSPs — compared with QICK (141 348 total LUTs, 877.5 BRAM, 2 049 DSPs), QubiC (51 665 total LUTs, 350 BRAM, 1 196 DSPs), and RISC-Q (71 930 total LUTs, 272 BRAM, 984 DSPs).

• Competitive normalized resource cost: After normalizing per qubit and per GHz, FIREQ reports 1 631.9 total LUTs, 998.9 logic LUTs, 21.2 LUTRAMs, 611.8 SRLs, 4 233.6 FFs, 8.8 BRAM, 0 URAM, and 39.0 DSPs — versus QICK (1 679.1, 1 410.1, 32.7, 236.3, 3 863.8, 15.5, 0, 32.7) and RISC-Q (2 145.5, 2 126.5, 0, 19.0, 4 471.5, 8, 0, 37). BRAM usage is comparable to RISC-Q's CORDIC-based approach, while the interpolation feature slightly raises DSP usage — a less constrained resource on the device.

• Qubit coherence validation: End-to-end operation on a superconducting qubit yields T₁ = 6.94 µs and T₂* = 13.50 µs.

• Shared generator design: Unlike QubiC (independent generators) and QICK (dedicated multiplexed-readout blocks), FIREQ reuses the same generator for drive and readout, combined with downstream multiplexing IPs, reducing the number of generator instances per qubit and avoiding per-pulse reconfiguration of modulation tones.

• Interpolation latency cost is small: The interpolation stage needs five clock cycles versus three for a direct LUT lookup, but because the DDS path runs in parallel and takes six cycles, the net end-to-end latency increase is only two cycles (3.2 ns). The linear interpolator is optimized to a single DSP slice using the UltraScale+ pre-adder.

• Memory trade-off from interpolation: Each generator has 16k I/Q samples of memory (compared to 32k for QICK full-throughput generators); because multiple samples must be produced per clock cycle, interpolation-mode envelopes are replicated across LUT banks, reducing effective memory to 1k I/Q samples. Generators can mix interpolated and as-is envelopes, and interpolation supports even and odd symmetry so only half the reference samples need storing.

• Acquisition buffering details: One URAM per acquisition IP stores up to 8192 decimated I/Q samples (a 14 µs acquisition window) or 4096 accumulated I/Q values (equivalent to 8 BRAM blocks); raw acquisition buffers in BRAM hold 2048 I/Q samples using 2 BRAMs per buffer.

• Timing engine capabilities: Up to 15 parallel triggers, each asserted for a single clock cycle, stored in an internal memory of up to 8096 entries, each specifying a relative delay and trigger set, with a maximum delay of approximately 7.35 seconds (longer delays by concatenation). The engine also generates shot- and experiment-level start/stop signals.

• Current channel scale: Two signal generation and acquisition peripherals are instantiated in the design, powering control of up to two qubits. Each generator stores up to 256 128-bit Wave-Definition Words, indexed by a memory-mapped FIFO holding up to 4096 indices.

• Not reported: The paper content does not report qubit frequencies, gate fidelities, number of shots per experiment, or a measured comparison of experiment throughput against the other frameworks. QubiC is excluded from the normalized per-qubit comparison because its Python-based meta-HDL framework obscures per-channel hierarchy, and HiSEP-Q 2.0 is excluded because a valid ZCU216 build could not be obtained from its public repository.

Methodology in Plain English

The team built a complete control system around a commercial RFSoC chip, which combines a processor, an FPGA fabric, and fast analog-to-digital and digital-to-analog converters on one die. Instead of using external mixers and analog IQ stages, the chip synthesizes and digitizes microwave signals directly.

The firmware is split into small, independently addressable blocks connected by a standard on-chip bus (AXI). A trigger generator schedules everything: an experiment is described in advance as a list of delays and trigger events, and each trigger launches a pulse or starts an acquisition. Pulse waveforms are stored as compact "wave definition words" in a small memory, with a separate first-in-first-out memory holding the order in which they play — so sequencing happens entirely in hardware without a soft-core processor in the time-critical path. A crossbar routes each pulse to chosen output converters, and a multiplexing block sums several generators onto one readout line.

Two ideas reduce memory pressure. First, pulse envelopes are stored sparsely and reconstructed on the fly by linear interpolation from a few reference samples, behaving like a digital synthesizer with first-order Taylor correction; this means a pulse's duration is decoupled from how many samples are stored, and symmetric envelopes only need half their samples. Second, acquired data that has already been decimated or accumulated is written to UltraRAM rather than the more bandwidth-limited BRAM, freeing BRAM for the raw high-speed stream.

On the software side, a host computer runs a client that turns a high-level experiment description into a hierarchical YAML-style configuration, serializes it with MessagePack, and sends it over TCP to a Python server running on the RFSoC. The server only does light validation, hardware configuration, execution, and acquisition handling, while heavier computation stays on the host. A producer–consumer design lets acquisition and data transfer run concurrently, and dependency-aware configuration updates avoid redundant recomputation during parameter sweeps.

Finally, the team compared resource usage against other open-source frameworks by building each from its public repository using its recommended or standard configuration, and they validated the whole chain on a real superconducting qubit with standard spectroscopy and coherence protocols.

Why This Matters

Impact on research: FIREQ provides an open, modular baseline that other groups can extend at the firmware level — swapping in custom signal-processing blocks without rewriting the higher software layers. Its low BRAM and logic footprint matters because, as the authors argue, scaling is constrained not just by channel count but by the hardware cost per channel, and eventually by power dissipation near cryogenic stages. It also gives quantum-hardware researchers a characterized environment for benchmarking alternative control and readout IP designs.

Real-world applications:

• Laboratory quantum computing testbeds that need multi-channel microwave control and readout at lower cost and rack space than AWG/mixer/digitizer stacks.
• Rapid prototyping of qubit calibration and characterization workflows (resonator spectroscopy, Rabi, Ramsey, T₁/T₂*), where repeated sweeps and fast data movement dominate experiment time.
• Educational and small-scale research labs building superconducting-qubit experiments from open-source hardware and software.
• Development and benchmarking of custom DSP or control IP for future cryogenic or integrated control electronics.

Industry relevance: The work targets the classical-control bottleneck that commercial quantum computing vendors face as qubit counts grow. Its emphasis on resource efficiency, standard AXI interfaces, and a clean client–server split aligns with industrial needs for reusable, reprogrammable control stacks, and its use of a mainstream AMD Zynq UltraScale+ RFSoC ZCU216 keeps it on commercially available hardware.

Future Directions

• Multi-board and multi-qubit scaling: Multi-board operation is listed as "Planned" in the framework comparison table, and the current design instantiates two generation/acquisition peripherals covering up to two qubits; extending to synchronized multi-board control is the obvious next step.
• Multiple readout output lines: The readout routing field is already propagated through the AXI Stream TUSER signals but is not yet used, reserved for future support of multiple readout lines.
• Wider IP ecosystem: Because the stated purpose includes evaluating alternative control and readout IP architectures, open questions include which signal-processing blocks (e.g., different carrier generation or demodulation schemes) most improve the resource/latency trade-off.
• Throughput benchmarking: The paper characterizes RF output (phase noise, noise spectral density, inter-channel timing skew) and resource usage, but a systematic comparison of experiment-level throughput and host–device overhead against QICK, QubiC, and RISC-Q is left open.

Target Audience

Quantum-hardware engineers and physicists building superconducting-qubit control electronics; FPGA and RFSoC developers interested in modular, resource-efficient instrumentation; research groups seeking an open-source alternative to commercial AWG/mixer/digitizer setups; and architects of higher-level quantum software stacks (such as Qibo-style gate-level interfaces) who need to understand what the underlying pulse-level hardware exposes.

Authors’ abstract

We present FIREQ (FPGA Instrumentation for Readout and Qubit control), an open-source RFSoC-based framework for the control and readout of superconducting qubits. FIREQ combines a modular AXI-compliant firmware architecture with a PYNQ-based software stack designed to support extensible hardware integration, deterministic experiment timing, and low-overhead execution of repeated calibration and characterization workflows. The firmware implements direct RF synthesis and acquisition, trigger-based sequencing, programmable pulse generation, frequency-multiplexed readout, and memory-efficient acquisition and waveform buffering. The software adopts a client-server architecture with streamed data transfer and dependency-aware configuration updates to reduce host-device and reconfiguration overhead during parameter sweeps. On an AMD Zynq UltraScale+ RFSoC ZCU216, FIREQ generates RF pulses up to 9.3 GHz with a pulse-duration resolution of 107 ps and an event-timing resolution of 1.7 ns. FPGA resource utilization is compared with representative open-source RFSoC control frameworks, showing a low BRAM footprint while retaining full-rate I/Q generation and acquisition. The RF output is characterized in terms of phase noise, noise spectral density, and inter-channel timing skew. End-to-end operation is validated on a superconducting qubit through resonator spectroscopy, Rabi, Ramsey, and relaxation measurements, yielding T1 = 6.94 us and T2* = 13.50 us. FIREQ can therefore be used both as a qubit-control platform and as an experimental environment for evaluating alternative control and readout IP architectures.