Fidelity-Aware Scheduling of Quantum Circuits on Multi-QPU Systems

AI summary

Overview

Research area: Quantum computing systems / HPC–quantum integration (quantum circuit compilation, device selection, and workload scheduling), with a machine-learning component (graph neural networks).

Technical level: Advanced. The paper assumes familiarity with quantum circuit compilation (qubit mapping, routing, native gate sets, transpilation), NISQ noise metrics, graph neural networks, and scheduling terminology. The prose is clear, but the content is aimed at specialists.

Scope (one sentence): The paper proposes and evaluates a framework that uses a graph neural network to predict, before compilation, how faithfully each circuit in a batch will execute on each available quantum processing unit, and feeds those predictions to a tunable scheduler that trades execution fidelity against load balancing across devices.

What This Paper Is About

Quantum computers are increasingly accessed as shared infrastructure that exposes several Quantum Processing Units (QPUs) differing in size, connectivity, native gates, and noise. A circuit's execution fidelity depends on which device it is compiled for, so choosing the right device matters — but determining the best device by compiling every circuit on every QPU costs k × D compilations for k circuits and D devices, while only k compiled circuits are ever executed. The paper's goal is to predict post-compilation fidelity directly from the high-level (uncompiled) circuit, then schedule circuits across QPUs using a single tunable weight that controls how strongly fidelity is prioritized over parallelism.

Key Contributions

1. An end-to-end framework integrating pre-compilation fidelity estimation with multi-circuit allocation, so each circuit is transpiled only for the device finally selected.
2. A GNN fidelity predictor that maps a circuit's Directed Acyclic Graph (with 40-element per-node feature vectors) to expected fidelity on each device; the graph encoder uses SAGE convolutional layers, optional bidirectional message passing, and a mean–max–sum pooling readout.
3. A tunable scheduling policy with a single fidelity weight w ∈ [0, 1], whose extremes are uniform round-robin (w = 0) and pure fidelity maximization (w = 1), applied sequentially over a shared circuit queue with load shares updated after each assignment.
4. An experimental evaluation on an emulated multi-QPU environment derived from real IQM superconducting devices (EQE1, 53 qubits, partitioned into 26- and 27-qubit sub-devices, plus QExa20, 20 qubits), compared against Oracle, ground-truth-weighted, and round-robin baselines.

Main Findings

• Accurate fidelity prediction: On the test set the model achieved overall MAE 0.0104 (reported as 1.04%), RMSE 0.0200 (2.00%), MSE 4.002 × 10⁻⁴, and R² = 0.9962.
• Per-device regression quality: EQE1 Top MAE 0.0105, RMSE 0.0205, R² 0.9959; EQE1 Bot MAE 0.0121, RMSE 0.0238, R² 0.9948; QExa20 MAE 0.0086, RMSE 0.0145, R² 0.9977.
• Error concentrated in a mid-fidelity band: Grouped by target fidelity, RMSE stayed below 4%, with the largest errors for circuits whose fidelities fall in [0.1, 0.4]; on QExa20 the RMSE was about 27.5% lower than the overall RMSE.
• Scheduler approaches the ground-truth upper bound: Across the 11-point sweep w ∈ {0.0, 0.1, …, 1.0} on the 5117-circuit test split, the GNN policy stayed within 0.0034 of the GT-Weighted upper bound at every weight.
• Fidelity range being contested is small in absolute terms: Round-Robin's overall mean ground-truth fidelity was 0.3436 and the Oracle's 0.3759 — a span of 0.032 on the [0, 1] scale.
• The dataset has a structural device bias: The Oracle sends 55.6% of circuits to EQE1_Bottom, 35.1% to QExa20, and only 9.3% to EQE1_Top (coefficient of variation CV = 0.697), i.e. 2846 circuits to EQE1_Bottom versus 474 to EQE1_Top.
• Tunability works as intended: The GNN policy's load CV goes from 0.0003 at w = 0 (identical to round-robin), to 0.033 at w = 0.3, 0.069 at w = 0.5, and 0.149 at w = 0.7 (where 1652, 1982, and 1483 circuits are distributed across the three backends); only near w = 1 does it collapse to the Oracle-like profile with CV = 0.884 and 3375 circuits on EQE1_Bottom.
• Agreement with the ground-truth policy: At w = 0.00 the GNN and GT-Weighted assignments agree 100.0% with zero regret; at w = 0.30 agreement is 68.8% with mean regret 0.0031 and median regret 0.0 (the table in the provided content is truncated beyond this row).
• Compilation savings: Because transpilation happens only for the selected device, the framework avoids the k × D compilation cost of exhaustive device selection while approximating exhaustive fidelity-based assignment.

Methodology in Plain English

The researchers define a circuit's expected fidelity on a device by multiplying together the calibrated success probabilities of every gate and readout operation in the compiled circuit — an approximation similar to Estimated Success Probability, which ignores idle-time decoherence, crosstalk, calibration drift, and shot noise. Because that quantity depends on compilation, they instead train a neural network to guess it from the circuit as written.

Each circuit is turned into a graph where nodes are gates and measurements and edges record which operations must happen in what order. Every node becomes a 40-number vector: 28 slots one-hot encode the operation type from the QASM3 gate set, 6 hold sine and cosine of rotation angles, and 6 describe structure (qubit count, control count, number of angle parameters, a critical-path flag, and predecessor/successor counts). A graph neural network using SAGE convolutions — optionally run forward and backward over the graph — reduces these to one vector per circuit, and a small multilayer perceptron outputs a fidelity estimate per device. Hyperparameters were tuned with Optuna over 50 trials (best: hidden_dim 142, 3 initial conv layers, 1 residual layer, dropout 0.0, bidirectional True, MLP (512, 256, 128), learning rate 10⁻³).

For scheduling, circuits are processed one at a time from a shared queue. Each candidate device gets a score of w × predicted_fidelity − (1 − w) × load_share, and the best-scoring device wins; the load counter updates immediately, so heavily chosen devices become progressively less attractive. At w = 0 this reduces to least-loaded selection (round-robin); at w = 1 to pure fidelity maximization. The authors show the ratio w/(1−w) acts as an exchange rate between fidelity advantage and load share. The policy is embedded in a Quantum Meta-Scheduler that snapshots queue and backend state each dispatch tick, transpiles each circuit only for its chosen device, submits it, and polls asynchronously.

Training data came from 17056 MQT Bench circuits across 35 categories, each compiled for all target devices with Qiskit at optimization level 2 to produce ground-truth labels. Splits were stratified: 70% training pool (further split 80/20 into training and validation), 30% held-out test.

Why This Matters

For NISQ-era hardware, errors compound quickly along a compiled circuit, so picking a mismatched device can meaningfully degrade results — yet the standard way to pick well (compile everywhere, then compare) wastes most of the compilation effort. This work shows that a learned pre-compilation estimate is accurate enough (R² of 0.9962 overall) to drive device selection, and that a single knob can make the system either quality-obsessed or throughput-friendly. It also quantifies a real tension: the fidelity-optimal assignment in their emulated environment sends most work to one device, leaving another nearly idle.

Real-world applications:

• Quantum cloud job submission: routing user-submitted circuit batches to the most suitable backend without paying for full multi-device transpilation.
• HPC–quantum integration: placing quantum kernels inside larger HPC workflows where turnaround time and device utilization matter alongside result quality.
• Shared quantum data centers: managing heterogeneous racks of QPUs with different technologies and calibration profiles.
• Workload planning and capacity studies: using predicted fidelity to reason about which hardware upgrades or partitions would actually help a given workload mix.

Industry relevance: Cloud quantum providers, HPC centers operating quantum resources, and hardware vendors exposing multi-QPU systems all face this placement problem; the tunable weight also gives operators a business-level lever between result quality and throughput.

Future Directions

• Generalization to other hardware: the authors state the predictor is not limited to the studied devices and can be regenerated for systems integrating devices with different technologies and gate sets.
• Better fidelity models: the current target ignores idle-time decoherence, crosstalk, calibration drift between snapshots, and shot noise — incorporating these, or refreshing predictions as calibrations change, is a natural extension.
• Scheduling beyond fidelity and load: queue times, execution duration, and backend availability are not part of the score and would matter in production dispatch.
• Scaling the study: the evaluation uses three emulated backends and 5117 test circuits; behavior with more QPUs, larger batches, and on real hardware rather than emulation remains to be shown.

Target Audience

Quantum computing systems researchers and compiler/scheduling engineers; HPC operators building hybrid quantum-classical infrastructures; practitioners applying graph neural networks to quantum circuit analysis; and graduate students or advanced undergraduates already comfortable with transpilation and NISQ noise concepts who want a concrete example of ML-driven resource management for quantum hardware.

Authors’ abstract

High Performance Computing-Quantum Computing (HPCQC) platforms expose multiple Quantum Processing Units (QPUs) that may differ in size, topology, native gates, and noise characteristics. For current noisy devices, errors compound along the compiled circuits quickly, and minimizing them, that is, maximizing the circuits' execution fidelity, is essential for reliable results. Fidelity depends on the compilation to a specific target device: the same high-level circuit may produce different executables and, therefore, different expected fidelities across QPUs. We present a low-overhead fidelity-aware scheduling framework for multi-QPU systems based on a Graph Neural Network (GNN) that estimates, before compilation, the expected fidelity of each circuit on each available QPU. Then, a tunable scheduler uses these estimates to control the trade-off between execution fidelity and parallelism. Results show that this framework allows for approximating an exhaustive fidelity-based assignment, saving computational resources compared to a brute-force approach that compiles each circuit on every device.