Exchange-only qubit stabilized by a single-spin qubit

AI summary

Overview

Research area: Quantum physics — semiconductor spin qubits, specifically hybrid architectures combining Loss–DiVincenzo (LD) single-spin qubits with exchange-only (EO) and singlet-only exchange-only (SOEO) qubits, plus low-level quantum error detection.

Technical level: Advanced. The paper assumes familiarity with spin-qubit encodings, stabilizer formalism, the [[4,2,2]] code, fault tolerance, and circuit-level noise simulation.

Scope (one sentence): The paper proposes and simulates a hybrid spin-qubit scheme in which auxiliary single-spin (Loss–DiVincenzo) qubits are used to read out the gauge degree of freedom of an exchange-only qubit and to perform fault-tolerant stabilizer readout of a singlet-only exchange-only qubit, converting charge and nuclear noise into erasures.

What This Paper Is About

Exchange-only qubits encode information in three spins and are controlled purely by exchange pulses, but their extra "gauge" degree of freedom is normally unused, and no fault-tolerant gate set had been established for them. The authors ask whether additional single-spin qubits — which could be available in spin-shuttling architectures — can be used to access that extra degree of freedom, to detect errors at the lowest encoding level, and to construct fault-tolerant gates. The goal is to show that a hybrid LD-plus-(S)EO architecture is a practical route to error detection compatible with shuttling-based quantum error correction.

Key Contributions

1. A gauge-transfer gate between an EO qubit and an LD qubit. Simultaneous exchange pulses of equal strength J between an LD spin (spin 4) and each of the three EO spins (1, 2, 3) generate, at gate time t_g = π/J, an iSWAP between the LD spin and the EO gauge qubit (S_z = ±1/2), using only exchange interactions.

2. A protocol that converts the EO qubit into a stabilizer-like monitored subsystem. Preparing the LD qubit in |↓⟩, applying U(t_g), and measuring the LD qubit implements the map ρ → A₀ρA₀† + A₁ρA₁†, where outcome |↓⟩ means the EO qubit was untouched (or leaked) and outcome |↑⟩ means it was projected into the {|0₋⟩, |1₋⟩} subspace.

3. Fault-tolerant stabilizer readout of the SOEO qubit using two LD auxiliary spins. The XXXX and ZZZZ stabilizers of the [[4,2,2]] code are measured with circuits that include a flag qubit, with the flag circuit verified to be fault tolerant against single physical faults.

4. Fault-tolerant π-rotations about all three SOEO control axes. Using an auxiliary spin, a SWAP (π-pulse) can be made fault tolerant; in the encoded SOEO basis, π-pulses on J₁₂, J₁₃, J₁₄ realize the logical operations Z_L, N_L, and M_L, with N_L = -(√3 X_L + Z_L)/2 and M_L = (√3 X_L - Z_L)/2.

Main Findings

• Gauge transfer is exact at t_g = π/J. For J = 100 MHz, the time evolution under the three simultaneous exchange couplings swaps the gauge information with the LD spin state; states |L_i⟩ (the four EO leakage states) are unaffected by the gate.

• Repeated projection can extend EO lifetime (Zeno-like). Averaged over k = 1, 2, 3 cycles and over the six input states {|0₋⟩, |1₋⟩, |0₋⟩±|1₋⟩, |0₋⟩±i|1₋⟩}, applying U(t_g) enhances the EO qubit lifetime when gate noise is low enough, consistent with the quantum Zeno effect. Idling noise was modeled as single-spin depolarizing with p_idle(t_g) = 3(1 - e^{-(t_g/T)²})/4 and T = 40 t_g; exchange noise was quasi-static with standard deviation σ, evaluated by Monte Carlo with 10⁴ runs.

• Flagged readout is fault tolerant with a pseudo-threshold of 3.5%. With single-spin depolarizing incoming faults, the unflagged QED error probability scales linearly and only slightly improves on no QED below p_spin = 0.02; the flagged circuit scales quadratically and yields a pseudo-threshold of p_spin = 3.5%.

• Weight-four incoming faults are partly invisible to the readout. Under a four-spin depolarizing channel, unflagged QED performs worse than not measuring stabilizers. Flagged QED reduces the qubit error by up to one order of magnitude below p_spin = 0.9%, shows quadratic behavior for p_spin ∈ [10⁻³, 10⁻¹], and approaches linear scaling for p_spin ≪ 10⁻³. Of 243 possible multi-weight faults, 63 are described as dangerous.

• Memory experiment shows logical lifetime improvement. With p_spin = 0.001 and one QED cycle taking t_c = 81 t_g, fits give logical decoherence times T_L = 3.20 × 10⁵ t_g (type-(i) idling, T = 1 × 10³ t_g) and T_L = 1.11 × 10⁵ t_g (type-(ii) idling, T = 4 × 10³ t_g). QED reduces the qubit error rate by up to two orders of magnitude for type-(i) decay and by almost one order of magnitude for type-(ii) decay.

• Trade-off between retention and fidelity depends on the noise spectrum. For type-(i) decay the QED acceptance rate exceeds the idling acceptance rate (suggesting Zeno stabilization); for type-(ii) decay QED lowers the acceptance rate while lowering the error rate of accepted runs.

• Fault-tolerant Z_L suppresses errors quadratically. Comparing direct versus fault-tolerant SWAP for Z_L, acceptance rates are comparable, but the fault-tolerant protocol scales quadratically rather than linearly, with up to two orders of magnitude suppression for p_spin ≈ 0.01%–1%. Results for N_L and M_L are stated to be equivalent.

• Only a partial fault-tolerant gate set exists. The authors identify only three single-qubit gates (Z_L, N_L, M_L) and the SWAP gate as fault tolerant in the SOEO encoding, which is far from a universal fault-tolerant gate set. N_L and M_L are noted to lie outside any finite level of the Clifford hierarchy; no fault-tolerant CNOT between two (S)EO qubits is established.

Methodology in Plain English

The work is entirely theoretical and simulation-based; no device data are reported.

• Encoding. Three spins in three quantum dots form an EO qubit holding a primary qubit and a gauge qubit; four spins in the S = 0 subspace form the SOEO qubit, whose stabilizers are XXXX and ZZZZ (the [[4,2,2]] code, encoding two logical qubits in four physical qubits at distance two).

• Gate construction. Because single-spin rotations are unavailable inside an EO/SOEO block, auxiliary LD spins supply single-qubit gates. √SWAP (π/2 exchange pulse) and SWAP (π exchange pulse) operations between spins implement the required entangling operations, and an extra auxiliary spin in an arbitrary state makes the SWAP fault tolerant.

• Noise modeling. Depolarizing noise with probability p_spin is applied per spin on initialization, on single-spin gates, and on two-spin gates; measurement error is modeled as a noisy Hadamard followed by perfect Z-basis measurement. Idling is modeled with two decay forms — 3(1 - e^{-(t/T)²})/4 and 3(1 - e^{-t/T})/4 — chosen as representative coherence scales motivated by silicon spin-qubit experiments.

• Fault-tolerance verification. Each noisy error-detection cycle is followed by a noiseless cycle, and postselection on trivial outcomes in both rounds checks that no single physical fault produces an undetected logical error. Simulations average over the input states {|0⟩, |1⟩, |+⟩, |−⟩, |i⟩, |−i⟩} (or the corresponding EO states), with Monte Carlo runs up to 10⁵ at the lowest error rates.

• Memory simulation. Repeated QED cycles plus idling are compared against pure idling, and the resulting error probabilities are fitted to decay functions to extract T_L and fitting coefficients (α = 0.83, β = 0.06, γ = 2.59, τ ≈ 6.06 × 10² t_g; and α = 0.33, β = 0.02, γ = 1.09, τ ≈ 1.25 × 10³ t_g).

Why This Matters

The work reframes the SOEO qubit as a logical encoding in its own right, not merely a three-spin qubit, and shows that error detection is available at the lowest hardware level without extra code overhead. Detected errors become erasures — a known route to higher surface-code thresholds — and reset-and-re-encode prevents errors from propagating into a higher-level code.

Potential applications:

• Silicon spin-qubit processors built from gate-defined quantum dots with exchange-only control, where exchange pulses avoid the heating and decoherence associated with strong driving fields.
• Spin-shuttling architectures, in which LD qubits are moved between (S)EO qubits and single-spin control zones, enabling arbitrary connectivity and the hybrid gates described.
• Surface-code fault-tolerant stacks, where (S)EO data and auxiliary qubits sit beneath a high-level code and low-level detection supplies erasure information and reduces the number of costly CNOT-based checks.
• Leakage mitigation, since the protocol reduces harmful leakage of both data and auxiliary SOEO qubits.

Industry relevance: The results target semiconductor-based quantum computing — a platform already compatible with established fabrication — and the paper notes that spin-qubit platforms have demonstrated gate fidelities exceeding 99% and small-scale processors. The proposal is architectural rather than device-specific, so its near-term relevance is as a design guide for hybrid spin-qubit layouts; no foundry or company-specific implementation is reported.

Future Directions

• A fault-tolerant CNOT between two EO or SOEO qubits. The authors explicitly leave open whether such a gate can be constructed, which is required for a universal fault-tolerant gate set.
• Additional fault-tolerant single-qubit gates. Beyond Z_L, N_L, M_L and SWAP, it is unknown whether further gates can be made fault tolerant using auxiliary spins.
• Exploiting the non-Clifford fault-tolerant gate. Because N_L and M_L lie outside any finite Clifford-hierarchy level, the authors suggest exploring whether this enables code switching or magic-state injection.
• Physical calibration and layout. The gauge-transfer gate requires a star-shaped coupling of one LD spin to all three EO spins at equal strength, which the authors note demands high-precision calibration; architecture designs incorporating fault-tolerant SWAPs and "phantom code" relabelling are proposed as future layout directions.

Target Audience

Graduate students and researchers in quantum information and semiconductor spin qubits, particularly those working on exchange-only encodings, spin-shuttling architectures, and fault-tolerant quantum error correction. Readers interested in hybrid qubit architectures or in mapping low-level error detection onto high-level codes will find the concrete circuits and noise simulations most useful; readers without stabilizer-code background will find Sections II.2 and II.3 demanding.

Authors’ abstract

Hybrid approaches that combine different spin qubit encodings offer promising advantages. In particular, the additional degrees of freedom available in exchange-only qubits and their extensions enable enhanced spin lifetimes and facilitate error detection through the use of auxiliary spins. We show that integrating Loss-DiVincenzo with exchange-only qubits provides a practical route to realizing these benefits while remaining compatible with spin-shuttling architectures. We further demonstrate how the singlet-only exchange-only qubit can be employed for error detection, and we present a fault-tolerant $π$-rotation about each of the three control axes of the (singlet-only) exchange-only qubit. By enabling error detection at the lowest encoding level, our approach effectively converts charge and nuclear noise into erasures, thereby suppressing error propagation and potentially enhancing the performance of quantum error-correction schemes. More broadly, our work establishes a new perspective on the singlet-only exchange-only qubit as a logical encoding, opening the door to fault-tolerant gate constructions and spin-tailored quantum error-correction protocols for semiconductor-based quantum computing.