Below-threshold execution of fault-tolerant ripple-carry addition on a trapped-ion quantum computer

AI summary

Overview

• Research area: Quantum computing — specifically early fault-tolerant quantum computing (EFTQC), quantum error correction (QEC), and fault-tolerant compilation of quantum arithmetic circuits on trapped-ion hardware.
• Technical level: Intermediate (leans advanced). Readers will get the most from it with some familiarity with stabilizer codes, transversality, and logical teleportation, though the central result — encoded circuits beating unencoded ones — is stated in plain terms.
• Scope: An experimental demonstration that a family of ripple-carry adder circuits, compiled onto an error-detecting-code architecture and run on Quantinuum's 98-qubit Helios-1 trapped-ion device, achieves lower failure rates than the same adders run unencoded for one- to three-bit inputs, with an algorithmic check (verifying reset of the initial carry qubit) as the key ingredient.

What This Paper Is About

Quantum computers make errors, and the standard fix is to encode each logical qubit across several physical qubits so errors can be detected and discarded. This paper asks whether that encoding actually pays off for a real, complete algorithm — integer addition — on today's hardware, rather than just for small benchmark circuits. The authors compile Cuccaro's ripple-carry adder onto an architecture built from two small error-detecting codes, run it on a trapped-ion machine for addends up to five bits, and compare encoded versus unencoded performance.

Key Contributions

1. A full compilation of ripple-carry addition onto a two-code EFTQC architecture. The authors take the Cuccaro et al. reversible adder (built from CNOT and Toffoli gates) and map it onto a universal gate set realized by code-switching between the [[8,3,2]] "smallest interesting colour code" and the [[4,2,2]] "iceberg" code, using transversal teleportation between blocks to obtain the needed logical Hadamards and CCZ gates.

2. Co-design of an "algorithmic check" with the error-detecting codes. The adder's initial carry qubit is provably restored to |0⟩ at the end of the circuit. Verifying this reset is a check that is independent of any QEC code but synergizes with it, raising the effective fault distance of many circuit locations from two to four.

3. A side-by-side physical-versus-logical experiment on Helios-1 for m = 1 through 5 bit addends, with resource counts reported at algorithmic, logical, and physical (guppy-program) levels. The authors note they did not have access to the final natively compiled circuits, so truly physical-qubit resource costs are not reported.

4. Identification and filtering of burst-error events by tracking shot survival versus circuit layer across batch jobs, and reporting failure rates both with all post-selected data and after discarding entire jobs flagged as anomalous.

Main Findings

• One-bit addition falls well below the physical failure rate. After burst-error filtering, the authors observed only a single logical failure in one-bit addition, giving an estimated logical failure rate of (6.0 ± 5.9) × 10⁻⁵, compared with (3.5 ± 1.3) × 10⁻³ for the same addition unencoded on the same hardware — a factor of more than 50. The error bar is large relative to the value because it rests on a single observed failure.

• Below pseudo-threshold for m ≤ 3, but only with the algorithmic check. Without the check, the logical circuits beat the physical ones only for single-bit addition. With the check, logical failure rates remained below physical failure rates through m = 3.

• Four- and five-bit adders executed just above threshold. At m = 4 the encoded algorithm performed slightly worse than the physical one; the m = 5 data departed from the trends seen for m = 1 to 4 for both logical and physical failure rates, and this was reproduced on different days with varying input bit strings.

• The algorithmic check helps logical circuits far more than physical ones. It improves physical failure rates somewhat, but its impact on the encoded circuits is much larger, which the authors attribute to its interaction with the error-detecting codes.

• The check extends effective fault distance from two to four. Because terminating measurements are all in the Z basis, only logical-X errors flip the outcomes, and the [[8,3,2]] code has an X-distance of four. Single logical-Z errors occurring between the Hadamards that conjugate CCZ into a Toffoli can become logical-X errors, but they propagate to the algorithmic-check qubit and are caught; at least two logical-Z errors are needed to pass undetected.

• Post-selection yield is the practical bottleneck. Post-selection rates start slightly above 60% at m = 1 and decay exponentially to approximately 1% at m = 5, while physical circuits using the algorithmic check stay above 95% throughout. The authors note the 98-qubit device could hold much larger instances, but the yield afforded by gate fidelities and the low code distance limits them to five bits.

• Burst errors are real and identifiable. Jobs implementing the same m-bit adder typically had comparable survival rates, but some jobs decayed much faster, indicating the hardware was not performing typically during those runs. Removing flagged jobs left fewer than three failures for m = 1 (one failure) and m = 2 (two failures), which is reflected in the error bars.

Methodology in Plain English

The team started with a textbook reversible adder: carry bits ripple upward through a chain of Majority subroutines, the final carry is copied out, then UnMajority-and-Add subroutines run back down, preserving the sum bits while restoring the input registers. That structure maps naturally onto their architecture — the CNOTs inside each subroutine become free qubit relabelings, and the Toffoli gates become short teleportation round-trips between the [[8,3,2]] block (which supplies a transversal CCZ) and the [[4,2,2]] block (which supplies a transversal Hadamard).

To keep noise exposure low, they made three practical changes: classical addends are prepared just in time rather than up front; each sum bit is measured immediately after its UnMajority gate, giving a "V"-shaped circuit; and the same four physical qubits are recycled for every short-lived [[4,2,2]] block. They also skipped active syndrome extraction between operations, relying only on the syndrome bits that fall out of the projective logical measurements (S₅ for the [[8,3,2]] code, S₂ for the [[4,2,2]] code).

Before running on hardware, they built Clifford "proxy" circuits — replacing each transversal CCZ with two transversal logical CZ gates — and simulated them on Helios-1E, Quantinuum's emulator with a noise model of Helios-1, in the guppy language. They tried several functionally equivalent program formulations because the proprietary compiler proved sensitive to how the program was expressed, and kept the best-performing one. On hardware they submitted jobs of at least 10³ and no more than 10⁴ shots, continuing until at least three failures were seen, with classical addends chosen uniformly at random (always including the all-ones value), and post-selected on all syndrome measurements plus the algorithmic check.

Why This Matters

This is a data point in the transition from the NISQ era to the early fault-tolerant era: it shows that small error-detecting codes can already pay for themselves on a real algorithm on real hardware, provided the algorithm offers its own redundant structure to exploit. The more transferable idea is the co-design insight — a redundant "gauge" degree of freedom in an algorithm can be turned into an error check that raises effective fault distance beyond what the codes alone supply. That suggests algorithm designers and QEC architects should look for such free checks rather than treating coding as a purely hardware-layer concern.

Potential application areas, framed by the paper as motivation rather than demonstration:

• Quantum algorithms built on arithmetic, which the authors identify as foundational building blocks; addition and carry propagation underpin modular-arithmetic routines used in cryptographic algorithms.
• Fault-tolerant compilation research, where the reported algorithmic/logical/physical resource counts for m-bit adders serve as a concrete cost baseline.
• Hardware benchmarking and yield planning, since the post-selection-yield curve (slightly above 60% down to about 1%) quantifies how much repetition overhead a device of this fidelity implies.
• Error-mitigation strategy design, where the burst-error identification method — tracking survival rate versus circuit layer per job — is a reusable diagnostic for cloud-accessed quantum hardware.

Industry relevance: The work is a collaboration between Sandia National Laboratories and the University of New Mexico, executed on commercially available trapped-ion hardware from Quantinuum. It speaks directly to vendors and users of early fault-tolerant machines about what encoded algorithm execution costs in shots and qubits today, and to compiler developers about the sensitivity of compiled output to source-level program structure.

Future Directions

• Add active syndrome extraction on idling logical qubits. The authors attribute the m = 4 shortfall to roughly O(m²) logical identity gates whose syndromes were never examined, and specifically flag the top logical qubit holding c₀, which undergoes O(m) logical identities between partial syndrome extractions and is expected to have an effective physical error rate O(m) times larger than the final carry qubit. They note they omitted these steps partly because doing so would reduce post-selection yield.
• Extend beyond classical inputs. The experiments used only classical addends; supporting quantum superpositions would require re-introducing the phase-reference qubit used by the architecture to track real and imaginary components for gates such as T = Z^{1/4}.
• Explain the m = 5 anomaly. The five-bit data consistently departed from the m = 1 to 4 trend across repeated runs, different days, and varied input strings, and the paper does not resolve why.
• Improve yield or raise code distance to scale past five bits. With 98 physical qubits available and at least 8m + 10 required for m-bit circuits, the limiting factor is post-selection yield rather than qubit count.

Target Audience

Quantum error correction and fault-tolerant architecture researchers; experimentalists running encoded algorithms on trapped-ion or superconducting hardware; quantum compiler engineers interested in how source-level program structure affects compiled performance; and graduate students in quantum information who want a concrete, honest case study of where encoded execution currently wins and loses against unencoded execution. Readers interested in the algorithmic-check idea specifically — using an algorithm's own invariant as a free error detector — will find it useful well beyond addition circuits.

Authors’ abstract

We deploy a universal fault-tolerant quantum computing (FTQC) architecture based on error-detecting $[\![8,3,2]\!]$ and $[\![4,2,2]\!]$ codes on Quantinuum's Helios-1 trapped-ion quantum computer. We compile and execute ripple-carry adder (RCA) circuits for classical inputs up to five bits on this architecture. Uncomputing a workspace qubit provides an additional ``algorithmic check'' to detect errors. While available at both the physical and logical levels, this check synergizes with our architecture by increasing the effective fault distance of many circuit locations from two to four. Combining this algorithmic check with the error-detecting codes, we observed only a single logical failure in one-bit addition after burst-error filtering, yielding an estimated logical failure rate of $(6.0 \pm 5.9) \times 10^{-5}$. This is well below the $(3.5 \pm 1.3) \times 10^{-3}$ failure probability observed for one-bit addition on the same hardware in unencoded form. Two- and three-bit adders also showed performance improvements, while the longer four- and five-bit adders executed just above threshold.