Accurate gap control of 3D-integrated superconducting quantum circuits using asymmetric indium architecture and multi-angle flip-chip bonding

AI summary

Overview

Research area: Superconducting quantum computing hardware, specifically three-dimensional (flip-chip) integration and packaging of superconducting qubit processors.

Technical level: Intermediate. The paper combines nanofabrication process engineering (lithography, indium evaporation, flip-chip bonding) with cryogenic microwave and qubit-coherence measurements. Readers with some familiarity with superconducting circuits will follow it easily; the fabrication details are dense but well separated into appendices.

Scope: The paper presents and evaluates an asymmetric indium flip-chip bonding process — thick indium bumps and SU-8 spacers confined to the control chip, thin indium pads on the qubit chip — combined with a four-step multi-angle compression routine, and quantifies the resulting inter-chip spacing accuracy, microwave loss, and transmon coherence.

What This Paper Is About

Scaling superconducting quantum processors beyond planar layouts requires stacking two chips face-to-face (flip-chip), so that qubits, readout resonators, and control wiring can be distributed across separate dies. The catch is that the vacuum gap between the two chips directly sets qubit capacitance, resonator frequency, and coupling strengths, so any unintended tilt or spacing variation after bonding shifts circuit parameters away from their designed targets. The authors ask whether an asymmetric indium architecture — avoiding thick indium and thick resist processing on the qubit chip altogether — plus a simple rotation-and-recompress bonding routine can deliver an accurately parallel, low-loss, coherence-preserving assembly.

Key Contributions

1. An asymmetric indium interconnect architecture. 20 µm thick indium bumps and ~10 µm SU-8 spacers are fabricated only on the control chip, while the qubit chip receives only 200 nm thick indium contact pads. This removes thick-resist lift-off and thick indium evaporation from the qubit-chip process, which follows a junctions-first, indium-pads-second sequence to protect the indium from harsh chemicals.

2. A multi-angle compression bonding procedure. After an initial compression at 16 N and room temperature, the bonded assembly is manually rotated and compressed again at nominal angles of π/2, π, and 3π/2 relative to the initial orientation, for four compression steps in total. This averages out a reproducible, bonder-induced systematic tilt.

3. Quantified spacing and tilt control across three bonding strategies and two chip sizes. Spacing is reconstructed from SEM edge measurements plus back-side profilometry of the qubit chip, yielding average spacing, rms spatial standard deviation, and the azimuthal/polar tilt angles for each process variant.

4. A loss and coherence audit of the process. CPW resonators on each chip, resonators with 1–6 indium transitions in the center conductor, and a six-transmon device measured both planar and flip-chip provide internal quality factors, a per-transition indium loss bound, and T₁/T₂,echo statistics.

Main Findings

• Spacers alone do not fix parallelism. Samples bonded without spacers reached a mean spacing of 9.97 µm but with an rms spatial standard deviation of 511 nm and an average polar tilt of θₐ = (248 ± 118) µrad. Adding SU-8 spacers of average height 10.28 ± 0.07 µm across a 4-inch wafer prevented over-compression, yet the rms standard deviation was still 418 nm and the tilt θ_b = (209 ± 84) µrad.

• The tilt has a systematic, reproducible direction. The azimuthal angles clustered near a preferred orientation: φₐ = (1.46 ± 0.10) rad without spacers and φ_b = (1.93 ± 0.07) rad with spacers, both near π/2 rad, which the authors attribute to the flip-chip bonder.

• Multi-angle bonding suppresses tilt by more than an order of magnitude. The polar tilt fell to θ_c = (20 ± 12) µrad, the azimuthal angle lost its preferred direction (φ_c = (−0.01 ± 1.71) rad), the mean spacing was 10.04 µm, and the rms spatial standard deviation dropped to 64 nm.

• The method holds at processor-relevant chip sizes. For 14.3 × 14.3 mm² dies (described as representative of chips for up to 20 qubits), four multi-angle assemblies gave φ_L = (−0.28 ± 1.09) rad, θ_L = (23 ± 8) µrad, mean spacing 10.08 µm, and rms spatial standard deviation 158 nm.

• Tilt translates into circuit-parameter error, and the process removes most of it. Simulations showed that a 2 µm spacing variation produces a 2% deviation in CPW resonator frequency and a 6% deviation in qubit capacitance, corresponding to a 6.5% variation in charging energy E_c and a 2.6% variation in qubit frequency. A 20 µrad tilt corresponds to only 0.2 µm of spacing deviation, keeping tilt-attributable deviations below 0.2% for resonator and qubit frequencies and below 1.1% for E_c.

• Measured parameter deviations before and after bonding are comparable. For the six-transmon device (planar target 4.5 GHz, flip-chip target 3.8 GHz), the average deviations were: readout resonator frequency −4.46 ± 0.54% (planar) versus −3.92 ± 0.34% (3D multi-angle); qubit frequency −2.08 ± 1.53% versus −1.20 ± 1.51%; charging energy −1.51 ± 0.17% versus −1.18 ± 0.59%. The differences are within the standard deviations, so the authors attribute the residual deviations to fabrication effects already present before bonding.

• The qubit-chip process yields a lower-loss microwave environment than the control-chip process. At high photon number, control-chip resonators reached Q_int = (4.81 ± 1.35)×10⁶ and qubit-chip resonators (7.47 ± 2.13)×10⁶. At low photon number these dropped to (0.90 ± 0.11)×10⁶ and (1.93 ± 0.40)×10⁶ respectively, consistent with unsaturated two-level-system loss.

• Indium transitions add little loss. Fitting the internal loss of resonators with one to six indium transitions in the center conductor gave δ_control = (9.19 ± 2.76)×10⁻⁷, δ_qubit = (3.01 ± 2.19)×10⁻⁷, and δ_In = (0.54 ± 0.42)×10⁻⁷ with R² = 0.68. Accounting for fit uncertainty, the per-transition loss tangent is bounded by δ_In < 1×10⁻⁷, an order of magnitude below the control-chip reference resonators' δ_ref = (1.03 ± 0.23)×10⁻⁶.

• Transmon coherence survives the process. Averaged over six qubits (f_q = (3.75 ± 0.06) GHz) and 100 measurements per qubit per parameter over 24 hours, the flip-chip device reached T₁ = (159 ± 14) µs — with individual qubits exceeding 200 µs — and T₂,echo = (294 ± 42) µs. A planar reference sample from the same process gave T₁ = (167 ± 34) µs across six qubits.

Methodology in Plain English

The authors deliberately split the fabrication burden between two chips. The control chip, which carries feedlines, drivelines, and fluxlines, gets the demanding processing: SU-8 epoxy spacers about 10 µm tall, hard-baked for mechanical stability, followed by a thick two-layer resist mask and thermal evaporation of roughly 20 µm of indium with an in-situ argon ion milling step to strip niobium oxide before deposition. The qubit chip — which hosts the Josephson junctions, qubits, couplers, and readout resonators — gets only a thin 200 nm indium pad evaporated through a 2 µm resist mask, after the junctions are already made. Both chips start from separate 100 mm high-resistivity silicon wafers with a 150 nm niobium ground plane patterned by optical lithography and SF₆ reactive-ion etching.

For bonding, the two dies are mounted in a commercial flip-chip bonder, optically aligned, and pressed together at room temperature with a 16 N normal force, so the indium plastically deforms and the native oxide fractures to form a galvanic contact. To test the tilt hypothesis, the team compares three groups: bonding without spacers, bonding with spacers in a single compression, and bonding with spacers where the assembly is rotated with tweezers to π/2, π, and 3π/2 and recompressed each time.

To measure how parallel the chips actually ended up, they use test dies sized 6 × 10 mm² and 6 × 8 mm² so the chip edges are coincident and both visible in one scanning electron microscope image, giving a direct edge-on spacing readout. Because SEM only sees the edges, they also profile the back side of the qubit chip across the full bonded area and reconstruct a spacing map, from which they extract average spacing, rms spatial standard deviation, and the two tilt angles.

Circuit parameters are checked by designing six transmons that can be measured first in a planar layout and then after flip-chip assembly, so each device serves as its own reference. Microwave loss is probed with λ/4 coplanar-waveguide resonators (50 Ω design, 10 µm center trace, 9 µm gaps, Q_c ≈ 5×10⁵) measured in a dilution refrigerator at roughly 15 mK, sweeping input power from −80 dBm to −160 dBm and extracting internal quality factors with a circle fit. A dedicated sample with one to six indium transitions along each resonator's center conductor isolates the loss per interconnect. Finally, qubit coherence is tracked continuously for 24 hours to capture temporal fluctuations rather than a single snapshot.

Why This Matters

Impact on research. The paper isolates tilt — rather than spacing offsets — as the dominant geometric error in indium flip-chip bonding, and shows a purely mechanical, low-cost fix. It also makes a concrete architectural argument: confining aggressive processing to the control chip measurably improves the qubit chip's microwave environment (7.47×10⁶ versus 4.81×10⁶ at high photon number), which is relevant to anyone deciding where to put which structures in a multi-chip stack. The per-transition indium loss bound of δ_In < 1×10⁻⁷ gives routing designers a number to budget against.

Real-world applications (as motivated by the paper's framing):

• Multi-chip superconducting quantum processors that need wiring density beyond what a single planar layout allows.
• Chip-to-chip microwave routing, where indium transitions in a center conductor let signals cross between dies.
• Process transfer to wafer-scale fabrication, since the thick-resist and thick-indium steps are designed to be run at wafer scale.
• Reference metrology for packaging: the SEM-plus-profilometry spacing reconstruction is a reusable quality-control method for any flip-chip assembly.

Industry relevance. Flip-chip bonding is already a standard back-end step in superconducting processor fabrication, and the hardware used here — a Finetech Fineplacer Femto2 bonder, PLASSYS evaporators, an Oxford PlasmaPro etcher, a Heidelberg MLA150 maskless aligner — is standard cleanroom equipment. The multi-angle routine requires no new tooling beyond manual rotation with tweezers, which makes it cheap to adopt. The demonstration at 14.3 × 14.3 mm² dies, sized for up to 20 qubits, targets exactly the scale at which foundry-style processors are being built.

Future Directions

• Automate the multi-angle routine. The manual rotation with cleanroom tweezers is the least scalable element; motorized, tool-integrated rotation with in-situ parallelism monitoring is the obvious next step, and would also clarify whether the residual 20 µrad floor is set by the bonder or by the resist spacers.

• Establish the residual tilt floor and its origin. The paper attributes the systematic tilt to the flip-chip bonder and leaves the offset between the final bonded spacing and the original spacer height to Appendix C; pinning down whether the remaining ~20 µrad and ~64 nm non-uniformity come from spacer height variation or indium creep would set the practical limit of the technique.

• Scale to larger and more complex stacks. Only 14.3 × 14.3 mm² dies and six-transmon devices are shown. Whether the tilt-averaging argument (which assumes the systematic deformation is reproducible across orientations) survives on much larger dies, or in stacks of more than two chips, is untested here.

• Test the architecture under realistic multi-qubit workloads. The coherence data come from six isolated transmons; two-qubit gate fidelities, crosstalk, and the behavior of qubits coupled through indium transitions in shared resonators are not reported.

Target Audience

Process and integration engineers working on superconducting qubit fabrication, quantum-hardware groups planning multi-chip architectures, and graduate students or postdocs entering the field who need a concrete, well-documented reference process for indium flip-chip bonding. It is also useful to cryogenic packaging specialists and to research managers evaluating whether flip-chip integration is mature enough for a given processor roadmap, since it reports packaging-induced parameter deviations alongside coherence metrics rather than only one or the other.

Authors’ abstract

Flip-chip 3D integration is a key enabling technology for overcoming the routing and layout constraints of planar superconducting quantum processors, but it requires accurate and uniform control of the inter-chip spacing while preserving qubit coherence. In conventional processes, thick indium bumps are deposited symmetrically on both chips, while dedicated spacers are introduced to limit the residual tilt. Here, we present a flip-chip bonding process based on an asymmetric indium architecture, combining $20\,μ\mathrm{m}$ thick indium bumps on the control chip with $200\,\mathrm{nm}$ thin indium pads on the qubit chip. Using electrical and microwave measurements, we demonstrate low resistance and low loss indium interconnects, and show that transmon qubits integrated with this process reach relaxation and coherence times of $T_1=(159\pm14)\,μ\mathrm{s}$ and $T_{\mathrm{2,echo}}=(294\pm42)\,μ\mathrm{s}$, respectively, comparable to planar devices. Combined with a multi angle compression procedure that suppresses systematic tilt, this approach reduces the average post bonding tilt to $(20\pm12)\,μ\mathrm{rad}$. These results establish an asymmetric indium architecture combined with multi angle compression as a robust, coherence preserving route toward 3D-integrated superconducting quantum processors.