A Modular, Topology-Aware Software Stack for Entanglement-Based Distributed Quantum Computing

AI summary

Overview

Research area: Distributed quantum computing — specifically the compilation and scheduling software layer that sits between quantum hardware (QPU interconnects, entanglement links) and high-level quantum programs.

Technical level: Advanced. The paper assumes familiarity with quantum circuits, gate/state teleportation, circuit DAGs, and graph/hypergraph partitioning. The prose is accessible, but the content is aimed at compiler and architecture researchers.

Scope: The paper presents an open-source, topology-aware framework that partitions a monolithic OpenQASM circuit across a user-specified network of QPUs, reconstructs it into a distributed program using teleportation-based primitives, and produces a time-resolved execution schedule under deterministic or stochastic entanglement generation.

What This Paper Is About

Building a useful distributed quantum computer requires splitting a single quantum program across multiple small processors linked by entanglement, then deciding when every local gate and every entanglement attempt should happen. Today's tools are split in two: monolithic circuit compilers that ignore networks, and long-distance quantum network simulators that ignore compilation. The authors build a single framework that connects the two ends of that gap, taking a standard circuit plus a description of the target hardware topology and emitting both a distributed OpenQASM program and a timestamped schedule.

Key Contributions

1. An end-to-end, open-source, topology-aware toolchain. Input is a standard OpenQASM circuit plus a JSON network description; output is a distributed OpenQASM program and a fully timed operation schedule. Because both ends speak standard OpenQASM, the framework interoperates with existing monolithic toolchains, simulators, and verification tools rather than replacing them.

2. The Quantum Network Constructor (QNC). A graphical tool for describing a network: per-QPU intra-connectivity, inter-QPU links between communication qubits, and link fidelity. It supports QPUs of differing qubit counts and topologies, and can build a module of only communication qubits that acts as a quantum router. It auto-generates the JSON file consumed by the compiler, and communication qubits are created automatically whenever an inter-QPU link is formed.

3. A modular partitioning layer with standardized interfaces. Every partitioning algorithm consumes the same two inputs (circuit DAG, network configuration) and emits the same output format: a matrix whose rows are circuit qubits and whose columns are execution time segments, with each entry naming the physical network qubit assigned. Two primary algorithms are provided — Dynamic Interaction partitioning (segment-based, adapted from Kaur et al., with Kernighan–Lin extended from a balanced bipartition to k parts under per-QPU capacity constraints) and Hypergraph partitioning (gate packets as hyperedges, partitioned with KaHyPar under per-QPU block-weight limits) — plus three additional benchmarking baselines. The authors state explicitly that these are adaptations of established methods to a hardware- and topology-aware setting, not novel partitioning algorithms.

4. Circuit reconstruction and scheduling. The compiler resolves cross-QPU gates using both state teleportation (as "remote swap" placeholders) and gate teleportation via Cat-Entangler/Cat-Disentangler packets, routes data qubits to communication qubits along each QPU's internal connectivity with local SWAPs, and emits all network primitives as named custom gates in a separate .inc file so a primitive's physical realization can be swapped without changing the program. The scheduler then assigns start and end times using either a discrete-event model with stochastic heralded entanglement "clicks" or a deterministic constant-time model, and can render the result as a Gantt chart or serialize it to JSON.

Main Findings

• No single best compilation strategy. The best-performing strategy varies across the tested circuits and network configurations, which the authors present as an argument against one-size-fits-all distributed compilation.

• Topology changes entanglement cost. Both the inter-QPU network topology and the intra-QPU connectivity of each processor substantially affect the EPR-pair cost of execution.

• EPR pairs are the dominant cost metric. Generating entangled pairs is far more time-intensive than executing local gates, so the framework's cost functions are denominated in EPR pairs: one pair per remote gate between directly connected QPUs, 1+2k pairs when the QPUs are separated by k intermediates, and 2h pairs for a remote swap over h hops (two per hop, one per state teleportation). Candidates with no valid route are assigned infinite cost.

• Segment length is a real trade-off, not a tuning detail. A small segment length ℓ allows frequent qubit relocation and can increase state teleportation; ℓ ≥ g for a circuit with g two-qubit gates collapses to a single static placement. The default is ℓ = clip([2√g], ℓ_min, ℓ_max) with ℓ_min = 10 (or 1 when g < 10) and ℓ_max = min(100, g). The authors state this heuristic is not guaranteed optimal and that the best value depends on both circuit and topology.

• Idealized-hardware assumptions limit prior work. The authors identify optimistic QPU-connectivity and network-topology assumptions, and poor generalization across representative circuits, as recurring weaknesses in prior partitioning work; their cost function explicitly prices routes through intermediary QPUs rather than assuming all-to-all connectivity.

• The open-source and scheduling gap. Among the distributed compilers surveyed (Pytket-DQC, Ferrari et al., Mengoni et al., and Kaur et al.), only Pytket-DQC is open source and none produces a time-resolved operation schedule; most do not give full control over both intra- and inter-QPU connectivity.

• Verification is bounded. The equivalence check compares measurement-outcome distributions using Qiskit simulators, either exactly from pre-measurement statevectors or by sampling with a Hellinger-fidelity threshold. Because statevector simulation requires storing 2^n amplitudes, verification is currently limited to circuits of up to 28 qubits.

• Quantitative benchmark results are not reported in the supplied text. The paper's demonstration section (Section V) is outside the content provided here, so no specific EPR counts, speedups, benchmark circuit names, or dataset sizes can be cited.

Methodology in Plain English

The workflow has four stages.

Preprocess. The input OpenQASM circuit is parsed, normalized, and turned into a directed acyclic graph where each node is an operation and each edge is a dependency. This DAG is cut into layers of operations that could run concurrently. Using OpenQASM as the front door means anything exportable to OpenQASM — for instance from Qiskit, or via the qBraid Transpiler — is supported automatically.

Partition. The circuit's qubits are assigned to physical QPUs in a way that respects each QPU's qubit capacity and the actual links between them. The Dynamic Interaction method slices the circuit into segments by two-qubit-gate count, builds an interaction graph for each segment (nodes are qubits, edge weights are interaction counts), and partitions it. For each new segment it compares the EPR cost of keeping the current placement against the cost of a new placement plus the cost of moving qubits there, accepting the new one only if it is cheaper. The Hypergraph method instead groups compatible two-qubit gates into "packets" that can share one entangled pair — a gate joins a packet only if it shares the packet's root control qubit, with special rules for symmetric cz gates, diagonal or anti-diagonal single-qubit gates on the control, and gates on targets. Packets become weighted hyperedges, so cutting one is priced at the true number of pairs it would consume rather than being overestimated.

Reconstruct. Walking the original circuit against the placement, any multi-qubit gate spanning QPUs is marked remote. Where a qubit changes QPU between segments, a state teleportation is inserted; because the software assumes per-QPU occupancy is constant and makes no assumption about buffer or memory qubits, a move from A to B is always paired with B to A, abstracted as a remote swap costing two pairs. Multi-hop moves follow the shortest path, and the module ensures no QPU exceeds capacity at any moment. Remote gates are then wrapped into Cat-Entangler/Cat-Disentangler packets, and any data qubit not adjacent to a communication qubit is walked to one with local SWAPs. A live logical-to-physical qubit map keeps every emitted gate pointed at the right hardware qubit.

Schedule. The distributed DAG, which captures all dependencies, is walked to assign timestamps. In stochastic mode, an EPR request triggers a simulated heralded "click" drawn from entanglement-generation rates before the remote operation can start; in deterministic mode every operation including entanglement generation takes a constant time. Either way the output respects all circuit dependencies and specifies exactly when each entanglement attempt, remote gate, and local operation occurs.

Why This Matters

Impact on research. The framework reframes distributed quantum compilation as a co-design problem spanning hardware specifications, network topology, compilation strategy, and scheduling policy, and gives the community a common, swappable substrate for comparing strategies. Standardized module interfaces mean a new partitioning algorithm can be dropped in and benchmarked without rebuilding the stack, and OpenQASM in/out means results stay comparable with monolithic toolchains.

Real-world applications:

• Designing data-center-scale quantum systems where many small processors are linked rather than one large one.
• Evaluating quantum interconnect and link-fidelity requirements before hardware is built, by sweeping topologies in the QNC.
• Planning long-range entanglement distribution and quantum-router architectures, using the communication-qubit-only module mode.
• Generating hardware-feasible, time-resolved schedules that can serve as an execution plan on real distributed hardware, not just a simulation artifact.

Industry relevance. For hardware vendors and cloud providers, the finding that no single compilation strategy wins across circuits and topologies argues for configurable, hardware-informed software rather than a fixed compiler pipeline. The explicit EPR-pair accounting gives a concrete cost signal for deciding how much interconnect fidelity and connectivity are worth.

Future Directions

• Fidelity and noise modeling. The stack deliberately does not model fidelity or noise, unlike SeQUeNCe and NetSquid; adding error models would connect schedules to realistic success probabilities.
• Decoherence, distillation, and physical effects. The authors list decoherence, entanglement distillation, and related phenomena as absent and left for future work.
• Scalable verification. The current equivalence check caps out at 28 qubits because of statevector memory; more scalable equivalence-checking techniques are flagged as open.
• Logical-level compilation and error correction. The framework targets NISQ-era programs and does not support QEC or logical-level compilation. Related open questions include how segment length ℓ should be chosen per circuit and topology, and whether the observation that the best strategy varies can be turned into an automatic strategy-selection policy.

Target Audience

Researchers and engineers working on distributed quantum computing, quantum compiler and transpiler development, and quantum network architecture. It is most useful to readers who want a ready-made experimental platform for comparing partitioning and scheduling strategies under realistic topology constraints, and to hardware architects who need to reason about how interconnect choices propagate up to program-level entanglement cost. Readers seeking new partitioning algorithms, noise-aware simulation, or error-corrected compilation will find those explicitly out of scope.

Authors’ abstract

Distributed quantum computing (DQC) seeks to scale beyond the limits of monolithic processors by interconnecting multiple quantum processing units (QPUs) through entanglement-based links. Realizing this vision requires the co-design of hardware and software across the domains of quantum networking, compilation, and scheduling, yet existing tools remain fragmented between monolithic circuit compilers and long-distance quantum network simulators. We present an open-source, topology-informed framework for the compilation and scheduling of distributed quantum programs. Given an input circuit and a description of the target network, the framework partitions and reconstructs the circuit into a distributed program that respects the specified inter- and intra-QPU topology, covers cross-QPU operations through gate and state teleportation, and schedules the result under either deterministic or stochastic entanglement-generation models. By accepting and emitting standard OpenQASM, the framework interoperates with existing monolithic toolchains, and its standardized module interfaces allow partitioning and scheduling strategies to be interchanged and benchmarked. Using this framework, we show that the best-performing compilation strategy varies across the tested circuits and network configurations, and that both network topology and intra-QPU connectivity substantially affect the entanglement cost of execution. These findings underscore the need for a co-design approach to distributed quantum computing, which our framework is designed to support.