The Signal
Mamba Decoder Cuts QEC Scaling to O(d²) in Real-Time Simulations
Changwon Lee, Tak Hur and Daniel K. Park report a Mamba-based quantum error-correction decoder with O(d²) computational scaling, compared with O(d⁴) for the Transformer decoder they studied. Tests on Google Sycamore memory data matched the
Quantum.world Team · Written with AI · fact-checked ·
A Mamba-based quantum error-correction decoder reached an effective error threshold of 0.0104 in the authors’ real-time simulations, compared with 0.0097 for a Transformer decoder. The study, published online on 28 October in npj Quantum Information, attributes the difference to decoding speed: its Mamba model has O(d²) computational scaling with code distance, against O(d⁴) for the Transformer architecture tested.
Changwon Lee, Tak Hur and Daniel K. Park also tested the Mamba model on memory-experiment data from Google’s Sycamore processor. They report matching the Transformer’s performance on that dataset, but the real-time advantage comes from simulations that add noise to represent errors accumulating while a decoder processes data. The paper does not demonstrate the decoder running in a live quantum processor’s control loop.
Sycamore data tests memory decoding
The hardware dataset comes from a 72-qubit superconducting processor with four distance-3 surface-code blocks and one distance-5 block. The experiments measured X- and Z-basis memories over as many as 25 error-correction cycles. The authors trained on half the Sycamore dataset and evaluated on the other half.
On the held-out data, the Mamba decoder’s logical error per round was about 2.98 × 10−2 at distance 3 and 3.03 × 10−2 at distance 5, which the paper says matched the Transformer-based decoder. The tensor-network decoder performed better at distance 5. Lee, Hur and Park attribute that gap in part to training data: their decoder used up to 100 million synthetic samples, while AlphaQubit had been pretrained on up to one billion.
“our Mamba decoder matches the performance of its Transformer-based counterpart”
Changwon Lee, Tak Hur and Daniel K. Park, “Scalable neural decoders for practical real-time quantum error correction”
Latency changes the simulated error rate
For the real-time comparison, the researchers simulated surface codes at distances 3, 5 and 7 using the SI1000 superconducting-circuit noise model. They injected additional depolarizing noise after each block of correction cycles, treating that noise as a stand-in for errors that build up while decoding takes time. Under this model, Mamba’s lower estimated computational cost produced a smaller latency penalty than the Transformer’s.
The threshold comparison is narrower than the distance-7 test: the reported 0.0104 and 0.0097 values come from the crossover in logical error rates between distances 3 and 5. They are effective thresholds in the study’s simulation, not measured operating limits for Sycamore or another processor. To calibrate its added-noise model, the paper uses a reported AlphaQubit decoding time of about 40 microseconds at distance 9 and assumes an induced error strength of 25p for the Transformer at that distance.
A scaling result, not a live decoder demonstration
The authors compared wall-clock inference time for Mamba and multi-head attention blocks on a local RTX 4090 GPU as code distance increased. Their headline complexity difference follows from the decoder design: surface-code syndrome data grows with d², while the Transformer’s attention compares inputs pairwise; Mamba instead updates a state as it processes the sequence. The paper presents that scaling as a route to lower decoding cost, rather than a measured end-to-end latency guarantee for a deployed system.
That distinction matters because a practical decoder must keep pace with the processor’s correction cycle, not merely outperform another model in a simulation. The reported Sycamore test establishes comparable memory-decoding performance on real hardware data; the latency-sensitive result depends on modeled decoder-induced noise. The next concrete test is whether an implementation can sustain the required cycle times on real control hardware while preserving the accuracy reported here.